Marie-Pierre Samson

Université Laval — Canada

Engineering · Physical Sciences

13h-index680citations43works0.02yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(32), Semiconductor materials and devices(30), Nanowire Synthesis and Applications(14), Ferroelectric and Negative Capacitance Devices(5), Integrated Circuits and Semiconductor Failure Analysis(5)

Publications43 total

Profils latents de traits de personnalité chez des couples en psychothérapie
Psycause revue scientifique étudiante de l École de psychologie de l Université Laval·2019Open Access
High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration
2017· 3 cited
Performance and design considerations for gate-all-around stacked-NanoWires FETs
2017· 147 citedOpen Access
Stacked-Wires FETs for Advanced CMOS Scaling
Extended Abstracts of the 2017 International Conference on Solid State Devices and Materials·2017· 3 citedOpen Access
Stacked-Wires FETs for advanced CMOS scaling
HAL (Le Centre pour la Communication Scientifique Directe)·2017Open Access
(Invited) Sequential 3D Process Integration: Opportunities for Low Temperature Processing
ECS Meeting Abstracts·2017
(Invited) Sequential 3D Process Integration: Opportunities for Low Temperature Processing
ECS Transactions·2017· 5 cited
Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains
ECS Journal of Solid State Science and Technology·2016· 4 cited
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
2016· 108 citedOpen Access
Atmospheric Pressure Selective Epitaxial Growth of Heavily in-situ Phosphorous-Doped Si(:C) Raised Sources and Drains
ECS Meeting Abstracts·2016
Integration of Low Temperature SiGe:B Raised Sources and Drains in p-Type FDSOI Field Effect Transistors
ECS Meeting Abstracts·2016
Integration of Low Temperature SiGe:B Raised Sources and Drains in p-Type FDSOI Field Effect Transistors
ECS Transactions·2016· 2 cited
Atmospheric Pressure Selective Epitaxial Growth of Heavily in-situ Phosphorous-Doped Si(:C) Raised Sources and Drains
ECS Transactions·2016
Stacked Nanowires FETs: Mechanical robustness evaluation for sub-7nm nodes
2016
(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities
ECS Transactions·2016· 11 cited
内部スペーサとSiGeソース/ドレインをもつ置換金属ゲートプロセスにおける垂直積層NanoWires MOSFET【Powered by NICT】
IEEE Conference Proceedings·2016
Opportunities and challenges of nanowire-based CMOS technologies
2015· 17 cited
A Novel Low Temperature (<500°C) and Low-κ (3.8) Boron Nitride PECVD Offset Spacer Featuring 3D VLSI Integration
Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials·2015· 2 cited
P-type trigate nano wires: Impact of nano wire thickness and Si<inf>0.7</inf>Ge<inf>0.3</inf> source-drain epitaxy
2015
Dual-channel CMOS co-integration with Si NFET and strained-SiGe PFET in nanowire device architecture featuring sub-15nm gate length
2014· 28 cited
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Frequent Co-authors

Sylvain Barraud(26), Jean‐Michel Hartmann(20), T. Skotnicki(18), S. Monfray(17), C. Vizioz(14), M. Vinet(13), F. Bœuf(13), C. Tabone(12), F. Allain(11), M. Cassé(11), R. Coquand(10), V. Maffini-Alvaro(9), C. Arvet(9), C. Fenouillet-Béranger(9), C. Comboroure(8), G. Ghibaudo(8), B. Prévitali(7), L. Gaben(7), P. Perreau(7), J. Bustos(7)