J. Kuss

IBM (United States) — United States

Engineering · Physical Sciences

16h-index794citations25works0.02yr avg
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Research Topics

Semiconductor materials and devices(23), Advancements in Semiconductor Devices and Circuit Design(21), Ferroelectric and Negative Capacitance Devices(8), Integrated Circuits and Semiconductor Failure Analysis(6), Silicon Carbide Semiconductor Technologies(3)

Publications25 total

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node
2014· 29 cited
Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
2014· 17 cited
High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
2013· 96 cited
Hole Transport in Strained and Relaxed SiGe Channel Extremely Thin SOI MOSFETs
IEEE Electron Device Letters·2013· 15 cited
UTBB FDSOI scaling enablers for the 10nm node
2013· 29 cited
UTBB FDSOI transistors with dual STI for a multi-V<inf>t</inf> strategy at 20nm node and below
2012· 53 cited
High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
2012· 74 cited
Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide
2012· 3 cited
Extremely thin SOI for system-on-chip applications
2012· 5 cited
Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
2012· 36 cited
Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length
IEEE Electron Device Letters·2011· 38 cited
Implant approaches and challenges for 20nm node and beyond ETSOI devices
2011· 7 cited
Enabling epitaxy on ultrathin implanted SOI
2011· 1 cited
Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications
2011· 2 cited
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm 2 SRAM cell
2011· 19 cited
Impact of back bias on ultra-thin body and BOX (UTBB) devices
2011· 45 cited
Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology
ECS Transactions·2011· 3 cited
Extremely thin SOI (ETSOI) technology: Past, present, and future
2010· 19 cited
Extremely-Thin SOI for Mainstream CMOS: Challenges and Opportunities
2010
Raised S/D for Advanced Planar MOSFET devices: Challenges and Applications for the 20nm Node and Beyond
2010
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Frequent Co-authors

B. Doris(25), A. Khakifirooz(19), S. Ponoth(17), Kangguo Cheng(16), P. Kulkarni(14), T. M. Levin(13), L. F. Edge(12), S. Kanakasabapathy(12), A. Reznicek(12), S. Schmitz(11), Steven J. Holmes(11), M. Vinet(11), Mukesh Khare(11), S. Luning(11), G. Shahidi(11), A. Upham(10), L. Grenouillet(10), S. Mehta(10), Walter Kleemeier(10), N. Loubet(9)