Ryuta Kawano

National Institute of Informatics — Japan

Computer Science · Physical Sciences

5h-index47citations32works0.02yr avg
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Research Topics

Interconnection Networks and Systems(24), Software-Defined Networks and 5G(10), Parallel Computing and Optimization Techniques(9), Advanced Memory and Neural Computing(7), Advanced Optical Network Technologies(7)

Publications32 total

Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks
2022
A traffic-aware memory-cube network using bypassing
Microprocessors and Microsystems·2022· 3 cited
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph
2021
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths
2021
Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method
IEICE Technical Report; IEICE Tech. Rep.·2021
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks
IEICE Transactions on Information and Systems·2020· 1 citedOpen Access
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks
2020
Low-Latency Memory Packet Network Using Bypassing
IEICE Technical Report; IEICE Tech. Rep.·2020
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks
IEICE Transactions on Information and Systems·2019Open Access
Deadlock-Free Layered Routing for Infiniband Networks
2019
A Scalable Multi-Path Selection Method for High-Throughput Interconnection Networks
IEICE Technical Report; IEICE Tech. Rep.·2018
k-Optimized Path Routing for High-Throughput Data Center Networks
2018· 6 cited
Measuring and Understanding Throughput of Routing Algorithms
IEICE Technical Report; IEICE Tech. Rep.·2018
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies
2017· 6 cited
A Layout-Oriented Routing Method for Low-Latency HPC Networks
IEICE Transactions on Information and Systems·2017· 7 citedOpen Access
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator
IEICE Transactions on Information and Systems·2017Open Access
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing
IEICE Transactions on Information and Systems·2017· 2 citedOpen Access
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies
2016· 5 cited
Body bias grain size exploration for a coarse grained reconfigurable accelerator
2016· 14 cited
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free
2016· 3 cited
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Frequent Co-authors

Hideharu Amano(31), Hiroki Matsutani(29), Michihiro Koibuchi(26), Hiroshi Nakahara(8), Ikki Fujiwara(8), Ryota Yasudo(7), Seiichi Tade(6), Fujiwara Ikki(5), Yoshiya Shikama(3), Yusuke Matsushita(2), Hayate Okuhara(2), Masuyama Koichiro(2), Yu Fujita(2), Yusuke Nagasaka(2), Naoto Fukumoto(2), Daichi Fujiki(1), Koji Nakano(1), Hiroki Tada(1), Tomohiro Ueno(1), Atsushi Koshiba(1)