G. Dermer

Intel (United States) — United States

Engineering · Physical Sciences

13h-index1.1kcitations22works0.02yr avg
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Research Topics

Low-power high-performance VLSI design(10), Semiconductor materials and devices(7), Parallel Computing and Optimization Techniques(6), VLSI and Analog Circuit Testing(5), Satellite Communication Systems(5)

Publications22 total

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)·2005· 2 cited
Bitline Leakage Compensation (BLC) and Leakage Reduction (BLR) Techniques for 23GHz On-Chip Cache Arrays in Microprocessors on 90nm Logic Technology
2005· 3 cited
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package
IEEE Journal of Solid-State Circuits·2005· 301 cited
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications
2005· 7 cited
A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control
2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551)·2004· 104 cited
Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops
2004· 15 cited
A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS
2004· 6 cited
Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique
2004· 84 citedOpen Access
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process
IEEE Journal of Solid-State Circuits·2004· 111 cited
Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation
2004· 153 cited
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process
2004· 67 cited
Microprocessor Power Optimization Through Multi-Performance
2004
A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS
IEEE Journal of Solid-State Circuits·2003· 45 cited
1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)·2003· 68 cited
A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)·2003· 8 cited
The Astronautics ZS-1 processor
2003· 4 cited
A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes
2002· 18 cited
5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS
IEEE Journal of Solid-State Circuits·2002· 35 cited
The ZS-1 central processor
ACM SIGOPS Operating Systems Review·1987· 2 cited
The ZS-1 central processor
ACM SIGARCH Computer Architecture News·1987· 79 citedOpen Access
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Frequent Co-authors

B. Bloechel(16), S. Narendra(13), Vivek De(13), Shekhar Borkar(13), P. Hazucha(8), Tanay Karnik(7), James Tschanz(7), Nitin Borkar(7), Sriram Vangal(6), Vasantha Erraguntla(6), K. Soumyanath(5), Dinesh Somasekhar(5), James E. Smith(5), B. D. Vanderwarn(5), Stefan Klinger(5), C. M. Rozewski(5), D. L. Fowler(5), K. R. Scidmore(5), James Laudon(5), V. Govindarajulu(5)