Tanay Karnik

Intel (United States) — United States

Engineering · Physical Sciences

44h-index8.1kcitations162works1.52yr avg
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Research Topics

Low-power high-performance VLSI design(64), Semiconductor materials and devices(56), Advancements in Semiconductor Devices and Circuit Design(31), VLSI and Analog Circuit Testing(27), Radiation Effects in Electronics(24)

Publications162 total

A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations
IEEE Journal of Solid-State Circuits·2025
Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration
2025
System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution
2025· 1 citedOpen Access
1.536TB/s/mm<sup>2</sup> Bandwidth Scalable Attention Accelerator with 22.5GOPS Throughput High Speed SoftMax for Quantized Transformers in Intel 3
2025· 1 cited
A High-Performance Passive Base System for Distributed AI/Media Acceleration
2025· 1 cited
A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System
2025· 1 cited
A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations
2025· 7 cited
A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology
IEEE Solid-State Circuits Letters·2025· 2 cited
A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems
2024· 2 cited
ISSCC 2024 Evening Event: EE5: The Legacy of Gordon Moore [Conference Reports]
IEEE Solid-State Circuits Magazine·2024
CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder
2023· 2 cited
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2023· 5 cited
Innovations for Intelligent Edge
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)·2022· 3 cited
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer
2022 IEEE International Symposium on Circuits and Systems (ISCAS)·2022· 2 cited
Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration
2022· 1 cited
Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems
2022 23rd International Symposium on Quality Electronic Design (ISQED)·2022· 6 cited
Session 13 Overview: Digital Techniques for Clocking, Variation Tolerance and Power Management
2022 IEEE International Solid- State Circuits Conference (ISSCC)·2022Open Access
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)
IEEE Journal of Solid-State Circuits·2021Open Access
Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration (Invited)
2021
Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation
2021· 13 cited
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Frequent Co-authors

Vivek De(30), Shekhar Borkar(20), P. Hazucha(18), James Tschanz(15), G. Schrom(10), Keith Bowman(9), Donald S. Gardner(9), Muhammad Khellah(9), S. Narendra(8), B. Bloechel(7), Fabrice Paillet(7), Paolo Aseron(6), Chris Wilkerson(5), G. Dermer(5), Arijit Raychowdhury(5), Carlos Tokunaga(5), Dinesh Somasekhar(5), A. Keshavarzi(4), Shih‐Lien L. Lu(4), Bibiche Geuskens(4)