R. Kies

Engineering · Physical Sciences

12h-index633citations45works0.02yr avg
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Research Topics

Semiconductor materials and devices(42), Advancements in Semiconductor Devices and Circuit Design(24), Advanced Memory and Neural Computing(18), Integrated Circuits and Semiconductor Failure Analysis(8), Electronic and Structural Properties of Oxides(7)

Publications45 total

Synergetic FeRAM/OxRAM memory array operation induced by oxygen vacancy interface engineering in Si:HfO2 ferroelectric films
2023
Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 1 citedOpen Access
7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing
2020· 95 cited
28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analysis
2020· 27 cited
All-Operation-Regime Characterization and Modeling of Drain Current Variability in Junctionless and Inversion-Mode FDSOI Transistors
2020· 15 cited
First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration
2020· 13 cited
7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing
IEEE Conference Proceedings·2020
Dense N over CMOS 6T SRAM cells using 3D Sequential Integration
2017· 3 cited
Influence of Low Thermal Budget Plasma Oxidation and Millisecond Laser Anneal on Gate Stack Reliability in view of 3D Sequential Integration
Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials·2016
Reliability of ultra-thin buried oxides for multi-VT FDSOI technology
Solid-State Electronics·2014
Leti Demonstrates Ultra-scaled Self-aligned Split-gate Memory Cell With 16nm Gate Length
2014
A technological and electrical study of self-aligned charge-trap split-gate memory devices
Microelectronic Engineering·2013· 4 cited
Lowering the Reset Current and Power Consumption of Phase-Change Memories with Carbon-Doped Ge2Sb2Te5
2012· 30 cited
Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length
2012· 6 cited
FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)
2012· 7 cited
Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- $k$ Control Dielectrics
IEEE Transactions on Electron Devices·2012· 11 cited
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
2011· 12 citedOpen Access
Investigation of charge-trap memories with AlN based band engineered storage layers
Solid-State Electronics·2011· 4 cited
Investigation of the role of H-related defects in Al<inf>2</inf>O<inf>3</inf> blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling
2010· 7 citedOpen Access
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
2010· 103 cited
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Frequent Co-authors

G. Ghibaudo(21), B. De Salvo(15), G. Molas(15), G. Pananakakis(13), M. Bocquet(12), M. Gély(11), X. Garros(9), P. Brianceau(9), A. Toffoli(8), G. Reimbold(8), P. Batude(8), C. Fenouillet-Béranger(7), J. P. Colonna(7), V. Vidal(7), C. Papadas(6), M. Cassé(6), B. Prévitali(6), G. Romano(6), L. Perniola(6), Elisa Vianello(6)