Kwanseo Park

Yonsei University — South Korea

Engineering · Physical Sciences

15h-index627citations58works0.82yr avg
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Research Topics

Advancements in PLL and VCO Technologies(43), Photonic and Optical Devices(27), Radio Frequency Integrated Circuit Design(19), Semiconductor Lasers and Optical Devices(12), Optical Network Technologies(9)

Publications58 total

A 28-Gb/s Receiver with Baud-Rate CDR Employing Integrated Pattern-Based Phase Detector Achieving ISI Invariant Phase Locking
2025
An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces
IEEE Transactions on Circuits and Systems I Regular Papers·2025
A 1.19-pJ/b 32-Gb/s Baud-Rate Receiver Employing 2UI Integrated Pattern-Based CDR and DFE Adaptation Without Data-Level Reference
IEEE Journal of Solid-State Circuits·2025
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology
IEEE Journal of Solid-State Circuits·2025
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver
IEEE Transactions on Circuits and Systems I Regular Papers·2025
A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver With Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS
IEEE Transactions on Circuits and Systems I Regular Papers·2025
A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2025· 1 cited
SSCS Seoul Chapter Members Gather at ISSCC 2025 [Chapters]
IEEE Solid-State Circuits Magazine·2025
IEEE SSCS Seoul Chapter Hosts DL Prof. Tetsuya Iizuka [Chapters]
IEEE Solid-State Circuits Magazine·2025
A 16-30Gb/s 1.03pJ/b Referenceless Baud-Rate CDR with Integrated Pattern Decoding Technique for Fast Frequency Acquisition
2024· 2 cited
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2024
A 0.07-pJ/bdB 32-Gb/s Receiver with Pattern-Based Baud-Rate CDR and DFE Adaptation Using 2UI Integrator without Data-Level Reference
2024· 2 cited
A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS
IEEE Transactions on Circuits & Systems II Express Briefs·2024· 3 cited
A 0.09-pJ/b/dB 28-Gb/s Digital CDR With ISI-Resistant Phase Detector
IEEE Transactions on Circuits & Systems II Express Briefs·2024· 2 cited
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS
2024· 1 cited
A Low-Jitter Phase Detection Technique With Asymmetric Weights in Multi-Level Baud-Rate CDR
IEEE Transactions on Circuits and Systems I Regular Papers·2024· 2 cited
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS
IEEE Transactions on Circuits and Systems I Regular Papers·2024· 1 cited
Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery
IEEE Transactions on Circuits & Systems II Express Briefs·2023· 4 cited
A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link
IEEE Access·2023· 2 citedOpen Access
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
IEEE Journal of Solid-State Circuits·2022· 14 cited
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Frequent Co-authors

Deog‐Kyoon Jeong(34), Kwang‐Ho Lee(13), Haram Ju(12), Jinhyung Lee(12), Woorham Bae(11), Sung‐Yong Cho(11), Han-Gon Ko(11), Minkyo Shim(8), Gyu-Seob Jeong(8), Jeongho Hwang(6), Min-Seong Choo(6), Hyo‐Jun Kim(5), Jaeduk Han(5), Sinho Lee(5), Minsoo Choi(4), Kyoungtae Lee(4), Zhaokai Liu(4), Ayan Biswas(4), Seungha Roh(4), Suil Kang(4)