Greg Stitt

University of Florida — United States

Computer Science · Physical Sciences

25h-index2.4kcitations127works0.82yr avg
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Research Topics

Embedded Systems Design Techniques(95), Parallel Computing and Optimization Techniques(88), Interconnection Networks and Systems(58), VLSI and FPGA Design Techniques(20), Low-power high-performance VLSI design(17)

Publications127 total

EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter
2026Open Access
Bridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications
2026· 1 citedOpen Access
Using FPGA devices to accelerate the evaluation phase of tree-based genetic programming: an extended analysis
Genetic Programming and Evolvable Machines·2025
It’s Time to Revisit the Use of FPGAs for Genetic Programming
Genetic and evolutionary computation·2025
Novel Toolset for Efficient Hardwired Micro-Op Translation in Embedded Microarchitectures
IEEE Embedded Systems Letters·2024· 1 cited
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet
2024· 3 citedOpen Access
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware
2023· 1 cited
Using FPGA Devices to Accelerate Tree-Based Genetic Programming: A Preliminary Exploration with Recent Technologies
Lecture notes in computer science·2023· 8 cited
Work-in-Progress: Toward a Robust, Reconfigurable Hardware Accelerator for Tree-Based Genetic Programming
2022
Dynamic Scheduling for Heterogeneous Multicores
SN Computer Science·2021· 1 cited
Scalable Performance Prediction of Irregular Workloads in Multi-Phase Particle-in-Cell Applications
2021· 1 cited
FPGA Acceleration of Fluid-Flow Kernels
2020· 2 cited
PANDORA
ACM Transactions on Embedded Computing Systems·2020· 6 cited
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development
2019· 7 cited
Energy Prediction for Cache Tuning in Embedded Systems
2019· 4 cited
Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction
2019· 2 citedOpen Access
Work-in-Progress: Offloading Cache Configuration Prediction to an FPGA for Hardware Speedup and Overhead Reduction
International Conference on Hardware/Software Codesign and System Synthesis·2019
Machine Learning-based Prediction for Dynamic Architectural Optimizations
2019· 3 cited
Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems
2019
Multi-Parameter Performance Modeling using Symbolic Regression
2019· 5 cited
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Frequent Co-authors

Frank Vahid(22), James Coole(7), Alan D. George(7), Walid Najjar(6), John Wernsing(5), Herman Lam(5), Jason Villarreal(5), Jeremy Fowers(4), Roman Lysecky(4), G.R. Brown(3), Dinesh C. Suresh(3), Patrick Cooke(2), Brian Grattan(2), Robert Kirchgessner(2), John Curreri(2), Aaron Landy(2), Shawn Nematbakhsh(1), Kalin Ovtcharov(1), Karin Strauß(1), Eric S. Chung(1)