Mark Kassab

Siemens (Germany) — Germany

Computer Science · Physical Sciences

17h-index2.1kcitations57works0.52yr avg
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Research Topics

VLSI and Analog Circuit Testing(53), Integrated Circuits and Semiconductor Failure Analysis(50), VLSI and FPGA Design Techniques(16), Engineering and Test Systems(13), Low-power high-performance VLSI design(8)

Publications57 total

Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies
Journal of Failure Analysis and Prevention·2025
Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies
Proceedings - International Symposium for Testing and Failure Analysis·2024· 1 cited
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations
2022· 1 cited
Efficient Test Compression Configuration Selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2021· 9 cited
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
2020· 6 cited
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
2020· 51 cited
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels
2020· 6 cited
Efficient Prognostication of Pattern Count with Different Input Compression Ratios
2020
Effective Design of Layout-Friendly EDT Decompressor
2020· 2 cited
Effective Design of Layout-Friendly EDT Decompressor
IEEE Conference Proceedings·2020
異なる入力圧縮比によるパターン計数の効率的予測【JST・京大機械翻訳】
IEEE Conference Proceedings·2020
TEA: A Test Generation Algorithm for Designs with Timing Exceptions
2019· 3 cited
Timing-Aware ATPG
2017
Isometric Test Data Compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2015· 19 cited
Hybrid Hierarchical and Modular Tests for SoC Designs
2015· 5 cited
Isometric test compression with low toggling activity
2014· 7 cited
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2014· 8 cited
Using dynamic shift to reduce test data volume in high-compression designs
2014· 6 cited
Test Compression Improvement with EDT Channel Sharing in SoC Designs
2014· 7 cited
Erratum to “Test Time Reduction in EDT Bandwidth Management for SoC Designs” [Nov 13 1776-1786]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2014Open Access
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Frequent Co-authors

Janusz Rajski(30), Jerzy Tyszer(21), Nilanjan Mukherjee(19), Wu-Tung Cheng(12), J. Rajski(11), Grzegorz Mrugalski(11), Xijiang Lin(9), S.M. Reddy(8), Kun-Han Tsai(7), Yu Huang(7), Jakub Janicki(6), N. Tamarapalli(4), Elham Moghaddam(4), Shi-Xuan Zheng(4), Kuen-Jong Lee(4), Jun Qian(3), Dhiraj Kumar Goswami(3), Chong-Siao Ye(3), Fong-Jyun Tsai(3), Chen Wang(3)