Kun-Han Tsai

Siemens (United States) — United States

Engineering · Physical Sciences

20h-index1.8kcitations80works1.02yr avg
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Research Topics

Integrated Circuits and Semiconductor Failure Analysis(68), VLSI and Analog Circuit Testing(66), 3D IC and TSV technologies(21), Engineering and Test Systems(12), VLSI and FPGA Design Techniques(11)

Publications80 total

Timing-Verification Test Generation Targeting Small Delay Defects
2025· 1 cited
Timing Critical Path Validation for Intel ATOM Cores Using Structural Test
2021
Test Challenges of Intel IA Cores
2020· 1 cited
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2019· 5 cited
TEA: A Test Generation Algorithm for Designs with Timing Exceptions
2019· 3 cited
Race and Glitch Handling: A Test Perspective
2019
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks
2019· 18 cited
GPGPU-Based ATPG System: Myth or Reality?
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2018· 3 cited
X-Sources Analysis for Improving the Test Quality
2018· 2 cited
Circuit and Methodology for Testing Small Delay Faults in the Clock Network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2018· 7 cited
Test Coverage Analysis for Designs with Timing Exceptions
2017· 5 cited
Online slack-time binning for IO-registered die-to-die interconnects
2016
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC
IEEE Design and Test·2016· 3 cited
A wide-range clock signal generation scheme for speed grading of a logic core
2016· 5 cited
Testing of small delay faults in a clock network
2016· 4 cited
Test coverage debugging for designs with timing exception paths
2016· 2 cited
Monitoring the delay of long interconnects via distributed TDC
2015· 5 cited
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects
IEEE Design and Test·2015· 2 cited
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2015· 9 cited
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2015· 6 cited
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Frequent Co-authors

Wu-Tung Cheng(25), J. Rajski(15), Shi‐Yu Huang(14), Malgorzata Marek-Sadowska(14), Janusz Rajski(7), Mark Kassab(5), Ruifeng Guo(5), N. Tamarapalli(4), Takeo Kobayashi(4), Li-Ren Huang(4), Stephen Sunter(4), Zhiyuan Wang(4), Yu-Hsiang Lin(4), Vishal Mehta(4), Yu Huang(3), Dhiraj Kumar Goswami(3), Meng‐Ting Tsai(3), Zeng-Fu Zeng(3), Brady Benware(2), Yasuo Satô(2)