Malgorzata Marek-Sadowska

University of California, Santa Barbara — United States

Engineering · Physical Sciences

42h-index6.5kcitations325works0.02yr avg
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Research Topics

VLSI and FPGA Design Techniques(175), Low-power high-performance VLSI design(158), VLSI and Analog Circuit Testing(144), Interconnection Networks and Systems(47), Embedded Systems Design Techniques(40)

Publications325 total

ISPD 2023 Lifetime Achievement Award Bio
2023
Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration
2019· 6 citedOpen Access
RAIN
2018· 16 cited
RAIN: A Tool for Reliability Assessment of Interconnect Networks—Physics to Software
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)·2018· 7 cited
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2018· 3 cited
An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation
2016· 5 cited
Making split-fabrication more secure
2016· 18 citedOpen Access
A fast, fully verifiable, and hardware predictable ASIC design methodology
2016· 2 cited
AFD-based model of EM lifetime and reservoir effect
2016· 2 cited
AFD-based method for signal line EM reliability evaluation
2016· 3 cited
Automated Routing for VLSI: Kuh's Group Contributions
IEEE Circuits and Systems Magazine·2016· 2 cited
Performance assessment of VeSFET-based SRAM
2015· 7 cited
Atomic flux divergence-based AC electromigration model for signal line reliability assessment
2015· 5 cited
Machine Learning in Simulation-Based Analysis
2015· 9 cited
Blech Effect in Interconnects
2015· 10 cited
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2015· 12 cited
Layout Aware Electromigration Analysis of Power/Ground Networks
2014· 3 cited
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2014· 12 cited
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2014· 2 cited
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs
2014· 1 cited
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Frequent Co-authors

Shih-Chieh Chang(6), Ashok Vittal(5), Kwang‐Ting Cheng(5), Chien-Chung Tsai(4), Amit Singh(3), Kai Wang(3), Bo Hu(3), Hailin Jiang(2), Chih-Chang Lin(2), Kuang-Chien Chen(2), L. P. P. P. van Ginneken(2), Forrest Brewer(2), Nam-Sung Woo(2), Y. Ran(2), Kun-Han Tsai(2), Janusz Rajski(2), E.S. Kuh(2), G. Parthasarathy(2), Yu‐Liang Wu(2), Liyuan Chen(1)