Shubin Liu

Xuzhou University of Technology — China

Engineering · Physical Sciences

19h-index1.5kcitations186works1.92yr avg
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Research Topics

Analog and Mixed-Signal Circuit Design(103), Advancements in Semiconductor Devices and Circuit Design(49), CCD and CMOS Imaging Sensors(46), Advancements in PLL and VCO Technologies(39), Low-power high-performance VLSI design(37)

Publications183 total

A 53 dB ripple reduction ratio, 0.68 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si4.svg" display="inline" id="d1e366"> <mml:mrow> <mml:mi>μ</mml:mi> <mml:msub> <mml:mrow> <mml:mi>V</mml:mi> </mml:mrow> <mml:mrow> <mml:mi>r</mml:mi> <mml:mi>m</mml:mi> <mml:mi>s</mml:mi> </mml:mrow> </mml:msub> </mml:mrow> </mml:math> noise bio-signal analog-front-end with a successive approximation ripple reduction loop
Microelectronics Journal·2025
Withdrawal notice to “A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator” [Microelectron. J. 166 (2025) 106872]
Microelectronics Journal·2025
Analysis and design of a sample-and-hold circuit with enhanced dual-noise-cancellation technique
Microelectronics Journal·2025
A full-rate 8.2-to-15.1-Gb/s reference-less CDR using low-cost SAR-based frequency acquisition technique achieving 265ns acquisition time
Microelectronics Journal·2025
Effects of biochar on phosphorus fraction, phosphatase activity, and phosphorus-solubilizing bacterial abundance: a phosphorus-depleted biochar design
Frontiers in Environmental Science·2025Open Access
A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator
Microelectronics Journal·2025
WITHDRAWN: A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator
Microelectronics Journal·2025
An Ultra-Compact 26/33 GHz Frequency-Reconfigurable Bi-Directional PA/LNA Front-End with &gt;33/&gt;24 dB Cross-Band Rejection
2025
A Ka-Band Bidirectional Active Phase Shifter with Reciprocal I/O Techniques Achieving &lt;1.9°/&lt;0.5dB RMS Phase/Gain Errors over 36% Bandwidth
2025
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units
Microelectronics Journal·2025
Load-driven inductive peaking design for broad band continuous-time linear equalizer
Microelectronics Journal·2025· 1 cited
A design of 96 GS/s 7-bit DAC for high-speed wireline transmitter in 28-nm CMOS
Microelectronics Journal·2025
A 0.0013-mm2 7-bit 2-GS/s time-domain 4-bit/cycle SAR ADC with the input-recoverable constant-current VTC
Microelectronics Journal·2025
A 10-16GHz Integer-N Ring PLL for Multi Lane SerDes
2025
A reference-free and derivative-insensitive all-digital calibration technique for timing-skew in TI-ADCs
Science China Information Sciences·2025· 2 cited
62dBc SFDR 1.52 GHz output DDFS utilizing real-time DCO calibration in 65 nm CMOS for radar and communication systems
Microelectronics Journal·2025
A Low-Noise Class-F <sub>23</sub> VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications
IEEE Transactions on Circuits and Systems I Regular Papers·2025
A 28–40 GHz 6-Bit Variable Gain Phase Shifter with &lt;0.4°/&lt;0.31 dB PS RMS Phase/Gain Errors and 31.5-dB Gain Tuning Range
2025
Design and analysis of an ultra-wideband quad-mode quad-core oscillator with mode ambiguity elimination
Microelectronics Journal·2025
Exponential-incremental quantization-based calibration for capacitor mismatch in high-precision SAR ADCs
Microelectronics Journal·2025· 1 citedOpen Access
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Frequent Co-authors

Zhangming Zhu(39), Yi Shen(14), Ruixue Ding(12), Longjie Zhong(7), Dengquan Li(6), Yanbo Zhang(5), Chi‐Hang Chan(5), Hongzhi Liang(5), Jin Zhang(4), Rong Zhou(4), Yuhua Liang(3), Yan Zhu(3), Donglai Xu(3), Haolin Han(3), Jiye Liu(3), Depeng Sun(3), Jingyu Wang(2), Xin Zhao(2), Xiyuan Tang(2), Xin Xin(2)