Jong Duk Lee

Engineering · Physical Sciences

18h-index1.3kcitations154works0.02yr avg
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Research Topics

Semiconductor materials and devices(79), Advancements in Semiconductor Devices and Circuit Design(61), Integrated Circuits and Semiconductor Failure Analysis(22), Thin-Film Transistor Technologies(19), Silicon Nanostructures and Photoluminescence(13)

Publications153 total

Growth and Physical Properties of GeSe2:In Films Prepared on Indium Tin Oxide
New Physics Sae Mulli·2011
Growth and Physical Properties of p-AgGaSe$_2$ Thin Films
New Physics Sae Mulli·2011
Growth Kinetics and Properties of Thin Cobalt Films Electrodeposited on n-Si(100)
Japanese Journal of Applied Physics·2010· 8 cited
Dumbbell-shaped Nanowire with Body Contact Region for Three Dimensional (3D) NAND Flash Memory Application
ICEIC : International Conference on Electronics, Informations and Communications·2010
A study on the carrier injection mechanism of the bottom-contact pentacene thin film transistor
Applied Physics Letters·2010· 27 cited
Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator
Japanese Journal of Applied Physics·2009
Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
Japanese Journal of Applied Physics·2009· 11 cited
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
IEICE Transactions on Electronics·2009· 1 cited
Dependence of Program Efficiency on Channel Conditions Regarding NOR-Type Flash Memory Devices Fabricated on a Silicon-on-Insulator (SOI) Substrate
Journal of the Korean Physical Society·2008· 1 cited
Structural and Optical Properties of ¥â-In2S3 and ¥â-In2S3:Co2+ Films Prepared on Indium-Tin-Oxide Substrates
Journal of the Korean Physical Society·2008· 10 cited
Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering(GIBL)
IEICE Technical Report; IEICE Tech. Rep.·2008
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
SIAM International Conference on Data Mining·2008
3-dimensional Terraced NAND (3D TNAND) Flash Memory
IEICE Technical Report; IEICE Tech. Rep.·2008
Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
SIAM International Conference on Data Mining·2008
A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current
2008· 4 cited
Dependency of Program Efficiency on Implementation Conditions for NOR Type Silicon-on-Insulator (SOI) Flash Memory
2008
Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator
Japanese Journal of Applied Physics·2008
Fabrication Process of Cone SONOS Memory Structure
ICEIC : International Conference on Electronics, Informations and Communications·2008
On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale Metal–Oixde–Semiconductor Field Effect Transistors
Japanese Journal of Applied Physics·2008· 3 cited
Dynamic bias temperature instability-like behaviors under Fowler–Nordheim program/erase stress in nanoscale silicon-oxide-nitride-oxide-silicon memories
Applied Physics Letters·2008· 9 cited
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Frequent Co-authors

Byung‐Gook Park(28), Jae Soo Yoo(9), Woo Young Choi(8), Sang Jik Kwon(6), Dae Hwan Kim(6), Hyungcheol Shin(5), Keum‐Dong Jung(4), Jae Sung Sim(4), Kyung Rok Kim(4), Cheon An Lee(3), Tae Hun Kim(3), Sung Hee Cho(3), Dong‐Wook Park(3), Ki‐Whan Song(3), Hyungcheol Shin(3), Byung Yong Choi(3), Seung Ho Kwon(2), Chang Woo Oh(2), Kun Jo Hong(2), Hyung Cheol Shin(2)