T. Futatsugi

Fujitsu (Japan) — Japan

Engineering · Physical Sciences

18h-index1.1kcitations69works0.02yr avg
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Research Topics

Semiconductor materials and devices(37), Semiconductor Quantum Structures and Devices(34), Semiconductor Lasers and Optical Devices(19), Quantum and electron transport phenomena(15), Advancements in Semiconductor Devices and Circuit Design(15)

Publications69 total

A study on millisecond annealing (MSA) induced layout dependence for flash lamp annealing (FLA) and laser spike annealing (LSA) in multiple MSA scheme with 45 nm high-performance technology
2009· 7 cited
Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects
2009· 25 cited
Copper wiring encapsulation at semi-global level to enhance wiring and dielectric reliabilities for next-generation technology nodes
2009· 1 cited
Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications
2008· 9 cited
High RF power transistor with laterally modulation-doped channel and self-aligned silicide in 45nm node CMOS technology
2008· 3 cited
Enhancing Yield and Reliability by Applying Dry Organic Acid Vapor Cleaning to Copper Contact Via-Bottom for 32-nm Nodes and Beyond
2008· 1 cited
Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond
2008· 3 cited
High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology
2007· 22 cited
Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform
2007· 2 cited
Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond
2007· 5 cited
Strategies of RC Delay Reduction in 45 nm BEOL Technology
2007· 7 cited
A 45nm Low-Cost LSTP CMOS Technology with full NCS/dual-damascene Cu interconnects
2007· 1 cited
A Direct Tunneling Memory (DTM) utilizing novel floating gate structure
2003· 2 cited
Compact and accurate quantum correction for MOS device simulator
2003· 2 cited
Room temperature operation of Si single-electron memory with self-aligned floating dot gate
2002· 17 cited
Dynamic properties of InAs self-assembled quantum dots for spectral hole burning memory application
2002
InAlAs/InGaAs double heterojunction bipolar transistors with a collector launcher structure for high-speed ECL applications
2002· 4 cited
Tetrahedral shaped recess channel HEMT with a floating quantum dot gate
2002
Spectral hole burning of InAs self-assembled quantum dots written by two different lasers
2002· 1 cited
Low threshold CW lasing of closely-stacked self-organized InAs/GaAs quantum dots
2002
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Frequent Co-authors

Naoki Yokoyama(32), Anri Nakajima(10), Naoto Horiguchi(10), Yuji Awano(9), Yoshihiro Nakata(6), T. Sugii(6), Shunichi Muto(6), A. Tsukune(6), H. Kurata(6), Yoshiki Sakuma(6), Yoshihiro Sugiyama(5), Tatsuya Usuki(5), Hiroshi Kudo(5), K. Kosemura(4), T. Fukano(4), Yoshiaki Nakata(4), Hiroshi Nakao(4), Hideki Kitada(4), H. Ochimizu(4), T. Owada(4)