Tao Chuan Lim

Institut d'électronique de microélectronique et de nanotechnologie — France

Engineering · Physical Sciences

9h-index272citations13works0.02yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(13), Semiconductor materials and devices(12), Radio Frequency Integrated Circuit Design(4), Ferroelectric and Negative Capacitance Devices(3), Silicon Carbide Semiconductor Technologies(2)

Publications13 total

Thermal Noise in MOSFETs: A Two- or a Three-Parameter Noise Model?
IEEE Transactions on Electron Devices·2010· 4 citedOpen Access
Experimental Investigation of RF Noise Performance Improvement in Graded-Channel MOSFETs
IEEE Transactions on Electron Devices·2009· 28 cited
Analog/RF Performance of Multichannel SOI MOSFET
IEEE Transactions on Electron Devices·2009· 49 cited
High frequency performance of sub-100nm UTB-FDSOI featuring TiN/HfO2 gate stack
Solid-State Electronics·2009· 2 cited
First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements
IEEE Electron Device Letters·2009· 19 cited
Impact of Lateral Asymmetry of MOSFETs on the Gate–Drain Noise Correlation
IEEE Transactions on Electron Devices·2008· 9 citedOpen Access
RF Small-Signal Analysis of Schottky-Barrier p-MOSFET
IEEE Transactions on Electron Devices·2008· 39 citedOpen Access
MOSFETs RF Noise Optimization via Channel Engineering
IEEE Electron Device Letters·2008· 20 cited
Scaling issues for analogue circuits using Double Gate SOI transistors
Solid-State Electronics·2007· 14 cited
Source/Drain Extension Region Engineering in Nanoscale Double Gate MOSFETs for Low-Voltage Analog Applications
Proceedings - IEEE International SOI Conference/Proceedings·2006· 6 cited
Performance Assessment of Nanoscale Multiple Gate MOSFETs (MuGFETs) for RF Applications
2006· 2 cited
The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance
Solid-State Electronics·2006· 42 cited
Parameter sensitivity for optimal design of 65nm node double gate SOI transistors
Solid-State Electronics·2005· 38 cited

Frequent Co-authors

F. Danneville(8), G.A. Armstrong(5), G. Dambrine(4), O. Rozeau(3), Jean‐Pierre Raskin(3), Émilie Bernard(2), T. Ernst(2), B. Guillaumot(2), Nathalie Vulliet(2), Michel Paccaud(2), Sylvie Lépilliet(2), RaphaËl Valentin(2), Mostafa Emam(2), P. Sakalas(2), Danielle Vanhoenacker-Janvier(2), Abhinav Kranti(2), C. Buj-Dufournet(1), Emmanuel Dubois(1), Guilhem Larrieu(1), N. Breil(1)