Jang-Gn Yun

Daelim University College — South Korea

Engineering · Physical Sciences

9h-index339citations82works0.02yr avg
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Research Topics

Semiconductor materials and devices(64), Advancements in Semiconductor Devices and Circuit Design(32), Semiconductor materials and interfaces(22), Advanced Memory and Neural Computing(17), Advanced Data Storage Technologies(16)

Publications82 total

Twin 2T0C DRAM Cells with Underlapped Gate-All-Around Write Transistor
Journal of Electrical Engineering and Technology·2025
High-density 3D-NAND flash with dual-string select line (D-SSL)
Engineering Research Express·2024Open Access
Improvement of Characteristics with a Sub-5 nm Ge-Doped Silicon Nitride Layer in Charge Trap Flash Memory Cells
Nanoscience and Nanotechnology Letters·2016
Effects of Gate/Blocking Oxide Energy Barrier on Memory Characteristics in Charge Trap Flash Memory Cells
Nanoscience and Nanotechnology Letters·2015
A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure
JSTS Journal of Semiconductor Technology and Science·2012· 9 cited
Abnormal oxidation in nickel silicide and nickel germanosilicide in sub-micro CMOS
Chinese Physics B·2012· 2 cited
Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray
IEEE Transactions on Electron Devices·2011· 77 cited
Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application
Solid-State Electronics·2011· 6 cited
LAyer Selection by ERase (LASER) With an Etch-Through-Spacer Technique in a Bit-Line Stacked 3-D nand Flash Memory Array
IEEE Transactions on Electron Devices·2011· 8 cited
Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory
IEEE Transactions on Electron Devices·2011· 29 cited
A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node
IEEE Transactions on Electron Devices·2010· 9 cited
Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
Japanese Journal of Applied Physics·2010
Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory
Japanese Journal of Applied Physics·2010· 13 cited
Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
Japanese Journal of Applied Physics·2010· 6 cited
Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance
IEEE Electron Device Letters·2010· 8 cited
Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
Japanese Journal of Applied Physics·2010· 2 cited
3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture
Solid-State Electronics·2010· 4 cited
Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
Japanese Journal of Applied Physics·2010· 21 cited
Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process
Japanese Journal of Applied Physics·2010· 9 cited
Scaling behaviors of silicon-nitride layer for charge-trapping memory
Journal of Vacuum Science & Technology A Vacuum Surfaces and Films·2010· 2 cited
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Frequent Co-authors

Byung‐Gook Park(30), Seongjae Cho(19), Yoon Kim(16), Hee-Hwan Ji(14), Bin-Feng Huang(12), Soon-Young Oh(12), Gil Sung Lee(11), Hi-Deok Lee(11), Han-Seob Cha(10), Jeong‐Gun Lee(10), Jin-Suk Wang(9), Se Hwan Park(8), Wandong Kim(8), Jong‐Ho Lee(8), Won‐Bo Shim(8), Doo-Hyun Kim(8), Hyungcheol Shin(7), Jung Hoon Lee(7), Il Han Park(6), Jung Hoon Lee(6)