Huiming Bu

Albany Molecular Research (United States) — United States

Engineering · Physical Sciences

11h-index833citations42works10.52yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(36), Semiconductor materials and devices(34), Ferroelectric and Negative Capacitance Devices(9), Nanowire Synthesis and Applications(8), Integrated Circuits and Semiconductor Failure Analysis(8)

Publications42 total

Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
2024· 5 cited
Backside Power Distribution for Nanosheet Technologies Beyond 2nm
2024· 16 cited
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
2023· 21 cited
Publisher Correction: The future transistors
Nature·2023· 1 citedOpen Access
The future transistors
Nature·2023· 480 cited
Next-generation logic design architecture for vertical-transport nanosheets
2023· 1 cited
CMOS Technology Beyond FINFET : Challenges and Opportunities
2022· 1 cited
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
ECS Meeting Abstracts·2021· 2 cited
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
ECS Transactions·2021· 14 cited
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
2020· 1 cited
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
2019· 5 cited
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
2019· 8 cited
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
2019· 25 cited
(Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors
ECS Meeting Abstracts·2018· 4 cited
Leakage aware Si/SiGe CMOS FinFET for low power applications
2018· 10 cited
低電力応用のための漏れを意識したSi/SiGe CMOS FinFET【JST・京大機械翻訳】
IEEE Conference Proceedings·2018
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
2017· 12 cited
SiGe FinFET for practical logic libraries by mitigating local layout effect
2017· 10 cited
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
2016· 10 cited
Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology
IEEE Electron Device Letters·2016· 58 cited
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Frequent Co-authors

Dechao Guo(19), Shogo Mochizuki(11), Veeraraghavan Basker(10), Miaomiao Wang(10), Tenko Yamashita(9), Pranita Kulkarni(9), Mukesh Khare(9), Juntao Li(8), Bala Haran(8), B. Doris(8), Hemanth Jagannathan(8), Huimei Zhou(8), A. Khakifirooz(7), Kangguo Cheng(7), Andreas Knorr(7), Dinesh Gupta(7), Zuoguang Liu(6), Oleg Gluschenkov(6), Nicolas Loubet(6), Curtis Durfee(6)