S. Vemulapalli

Texas Instruments (United States) — United States

Engineering · Physical Sciences

11h-index1.4kcitations18works0.02yr avg
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Research Topics

Advancements in PLL and VCO Technologies(15), Radio Frequency Integrated Circuit Design(12), Analog and Mixed-Signal Circuit Design(7), Semiconductor Lasers and Optical Devices(5), Photonic and Optical Devices(2)

Publications18 total

Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches
2011· 5 cited
Spur-free all-digital PLL in 65nm for mobile phones
2011· 26 cited
A 0.8mm<sup>2</sup> all-digital SAW-less polar transmitter in 65nm EDGE SoC
2010· 25 cited
An all-digital offset PLL architecture
2010· 11 cited
Elimination of spurious noise due to time-to-digital converter
2009· 16 cited
A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS
2009· 10 cited
A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS
2008· 62 cited
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process
IEEE Journal of Solid-State Circuits·2006· 112 cited
Yield Aware Design Methodology for Sub-100-Nanometer Digital SOC Designs
2006
Implementation of a High Speed Digital Band-Pass Sigma-Delta Modulator for a Wireless Transmitter
2006· 6 cited
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing·2006· 327 cited
A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process
2006· 45 cited
All-digital PLL and transmitter for mobile phones
IEEE Journal of Solid-State Circuits·2005· 619 cited
All-digital PLL and GSM/edge transmitter in 90nm CMOS
2005· 143 cited
Time-to-digital converter for RF frequency synthesis in 90 nm CMOS
2005· 36 cited
Multiple antenna techniques for pulse-based ultra-wideband system
Annals of the New York Academy of Sciences·2004
A voice processing and control module for cable telephony applications
2003
Dual-Crosshatch Disk Array: A Highly Reliable Hybrid-RAID Architecture.
1995· 4 cited

Frequent Co-authors

Robert Bogdan Staszewski(20), J. Wallberg(10), Oren Eliezer(10), Chih-Ming Hung(8), P. Cruise(7), C. Fernando(6), K. Maggio(6), Dirk Leipold(6), S. Rezeq(5), Mitch Entezari(5), K. Muhammad(5), Khurram Waheed(5), N. Barton(4), Poras T. Balsara(4), T. Mayhugh(4), T. Jung(4), I. Elahi(4), I. Deng(4), Shawn D. Larson(4), Thomas W Murphy(4)