K. Itoh

National Yang Ming Chiao Tung University — Taiwan

Engineering · Physical Sciences

32h-index3.2kcitations122works0.02yr avg
OpenAlex↗Google Scholar↗Lab page↗

Accepting Students?

No reports yet. Know if this professor is taking students?

Research Topics

Semiconductor materials and devices(84), Advancements in Semiconductor Devices and Circuit Design(77), Low-power high-performance VLSI design(55), Advanced Memory and Neural Computing(15), Liquid Crystal Research Advancements(14)

Publications122 total

Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line
2019
Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays
2010· 8 cited
FD-SOI MOSFETs for the low-voltage nanoscale CMOS era
2009· 11 cited
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs
2007· 15 cited
Impact of FD-SOI on Deep-Sub-100-nm CMOS LSIs -A View of Memory Designers-
Proceedings - IEEE International SOI Conference/Proceedings·2006· 5 cited
Ultra-Low Voltage Nano-Scale Embedded RAMs
2006· 15 cited
Reviews and Prospects of Low-Voltage Nano-Scale Embedded RAMs
2006
A 0.4-V High-speed, Long-retention-time DRAM Array with 12-F/sup /2 Twin Cell
2005
Dynamic-Vt, dual-power-supply SRAM cell using D2G-SOI for low-power SoC application
2005· 5 cited
Low-voltage embedded RAMs in the nanometer era
2005· 10 cited
Trends in low-voltage embedded RAMs
The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.·2004· 1 cited
Ultralow-voltage RAM technology - current status and future trends
2004
Review and future prospects of low-voltage RAM circuits
IBM Journal of Research and Development·2003· 161 cited
Trends in low-voltage embedded-RAM technology
2003· 10 cited
A 60 nm channel length silicon stacked tunnel transistor
2003· 1 cited
A 1.5 V DRAM for battery-based applications
2003· 19 cited
Trends in megabit DRAM circuit design
International Symposium on VLSI Technology, Systems, and Applications·2003· 5 cited
A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure
2003· 22 cited
A single 1.5-V digital chip for a 10/sup 6/-synapse neural network
2003· 3 cited
Sub-1-V swing bus architecture for future low-power ULSIs
2003· 29 cited
page 1 of 7Next →

Frequent Co-authors

Y. Nakagome(13), Masakazu Aoki(12), Y. Kawamoto(9), Masashi Horiguchi(9), Eiji Takeda(8), J. Etoh(8), Kazuhiro Takeuchi(7), H. Sunami(7), T. Toyabe(7), S. Kimura(6), R. Hori(6), T. Kure(6), Hideo Takezoe(5), Atsuo Fukuda(5), N. Hashimoto(5), Y. Kawajiri(5), Digh Hisamoto(4), T. Kawahara(4), Yukio Ouchi(4), T. Sakata(4)