T. Sakata

Mitsubishi Electric (Japan) — Japan

Engineering · Physical Sciences

12h-index487citations39works2.02yr avg
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Research Topics

Semiconductor materials and devices(23), Advancements in Semiconductor Devices and Circuit Design(17), Low-power high-performance VLSI design(16), Advanced Memory and Neural Computing(6), Ferroelectric and Negative Capacitance Devices(6)

Publications39 total

High-quality and high-resolution thin-wall fabrication of A5183 aluminum alloy using wire-laser metal 3D printer
The International Journal of Advanced Manufacturing Technology·2025· 2 citedOpen Access
Influence of Processing and of Material Defects on the Electrical Characteristics of SiC-SBDs and SiC-MOSFETs
Materials science forum·2010· 21 cited
Voltage-Current (V-I) Characteristics of 1.5kV Class pn Junctions with p-Well Structures on (0001) 4H-SiC
Materials science forum·2009· 1 cited
Defect-Free Epitaxial Lateral Overgrowth (ELO) Technique For Future Generation Low Power CMOSFETs
Proceedings - IEEE International SOI Conference/Proceedings·2006
Basic study on acoustic noise of polluted insulator and waveform analysis method
2005· 4 cited
A 4.8-ns random access 144-Mb twin-cell-memory fabricated using 0.11-μm cost-effective DRAM technology
2004· 6 cited
A robust array architecture for a capacitorless MISS tunnel-diode memory
2003
A single 1.5-V digital chip for a 10/sup 6/-synapse neural network
2003· 3 cited
The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory
2002· 2 cited
A small data-line-swing read/write scheme for high-endurance nonvolatile DRAMs with ferroelectric capacitors
2002· 2 cited
Prober for highly integrated multichip modules
2002· 2 cited
An experimental 220 MHz 1 Gb DRAM
2002· 29 cited
Reviews and prospects of high-density RAM technology
2002· 10 cited
Phase-state low electron-number drive random access memory (PLEDM)
2002· 16 cited
CMOS-logic-circuit-compatible DRAM circuit designs for wide-voltage and wide-temperature-range applications
2002· 3 cited
A DDR/SDR-compatible SDRAM design with a three-size flexible column redundancy
2002· 3 cited
MISS tunnel diode: a capacitorless 4F/sup 2/ memory cell for sub-0.1 μm era
2002
A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
IEICE Transactions on Electronics·2002
A High-Endurance Read/Write Scheme for Half-V~c~c Plate Nonvolatile DRAMs with Ferroelectric Capacitors
IEICE Transactions on Electronics·2001· 1 cited
An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
2001· 1 cited
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Frequent Co-authors

Masakazu Aoki(11), Masashi Horiguchi(9), K. Itoh(9), Tomonori Sekiguchi(6), K. Kajigaya(5), Hitoshi Tanaka(4), K. Kimura(4), Y. Nakagome(4), Takao Watanabe(4), O. Nagashima(4), Hironori Fujisawa(4), Tomoko Sekiguchi(4), Koji Kimura(4), S. Ueda(3), T. Kisu(3), Takashi Nishida(3), Kiyoo Itoh(3), S. Kimura(2), E. Yamasaki(2), M. Ohkura(2)