K. Koyama

Engineering · Physical Sciences

12h-index526citations37works0.02yr avg
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Research Topics

Semiconductor materials and devices(23), Advancements in Semiconductor Devices and Circuit Design(12), Advancements in PLL and VCO Technologies(6), Integrated Circuits and Semiconductor Failure Analysis(5), Low-power high-performance VLSI design(4)

Publications37 total

Enhancing Interactivity in Handheld AR Environments
2011
Low complexity real-time video transcoders for mobile video applications
2008
Low Complexity Real-Time Video Transcoders for Video Upload and Retrieval Applications
SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems·2007· 1 cited
B-6-90 Development of MRF for NGN/IMS
Proceedings of the IEICE General Conference·2007
VECTORIZATION AND PRECISE REFRACTIONS IN BEAM TRACING
International Journal of Image and Graphics·2004
A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer
IEEE Journal of Solid-State Circuits·2003· 65 cited
Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 μm-scale embedded DRAM
2003· 5 cited
A 55 ns 16 Mb DRAM
2003· 6 cited
A boosted dual world-line decoding scheme for 256 Mb DRAMs
2003· 11 cited
A 0.23 μm/sup 2/ double self-aligned contact cell for gigabit DRAMs with a Ge-added vertical epitaxial Si pad
2002· 2 cited
Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM
2002· 1 cited
A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors
2002· 28 cited
1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET
2002· 12 cited
A stacked capacitor with (Ba/sub x/Sr/sub 1-x/)TiO/sub 3/ for 256M DRAM
2002· 12 cited
A 4-level storage 4 Gb DRAM
2002· 25 cited
Two-dimensional borderless contact pad technology for a 0.135 μm/sup 2/ 4-gigabit DRAM cell
2002· 4 cited
Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure
2002· 3 cited
A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs
2002· 3 cited
Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation
2002· 1 cited
A 1 Gb DRAM for file applications
2002· 23 cited
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Frequent Co-authors

T. Murotani(7), N. Kasai(6), Kentaro Shibahara(5), T. Tanigawa(5), Y. Takaishi(5), T. Matano(4), H. Mori(4), S. Iwao(4), T. Tatsumi(4), K. Ozawa(4), T. Saeki(3), Toshiro Itani(3), Takashi Okuda(3), T. Takeshima(3), Hiroki Koike(3), Y. Aimoto(3), Midori Takada(3), H. Hada(3), S. Ohya(3), K. Saino(3)