Yung-Fa Chou

ITRI International — United States

Engineering · Physical Sciences

15h-index835citations73works0.02yr avg
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Research Topics

3D IC and TSV technologies(38), VLSI and Analog Circuit Testing(30), Integrated Circuits and Semiconductor Failure Analysis(25), Semiconductor materials and devices(20), Low-power high-performance VLSI design(9)

Publications73 total

Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method
2020
Time-to-Digital Converter Compiler for On-Chip Instrumentation
IEEE Design and Test·2020· 6 cited
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction
2018· 11 cited
A channel-sharable built-in self-test scheme for multi-channel DRAMs
Asia and South Pacific Design Automation Conference·2018· 1 cited
A channel-sharable built-in self-test scheme for multi-channel DRAMs
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)·2018· 1 cited
3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)
IEEE Journal of the Electron Devices Society·2018· 16 citedOpen Access
DLL-Assisted Clock Synchronization Method for Multi-Die ICs
2017· 5 cited
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs
2017· 6 cited
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC
2017· 3 cited
Resilient Cell-Based Architecture for Time-to-Digital Converter
2017· 6 cited
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache
2017· 8 cited
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization
2017· 1 cited
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits
2016· 15 cited
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
2016· 4 cited
Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration
2016· 3 cited
Testing power-delivery TSVs
2015· 3 cited
Temperature-aware online testing of power-delivery TSVs
2015· 1 cited
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
2015· 5 cited
Hierarchical Test Integration Methodology for 3-D ICs
IEEE Design and Test·2015· 6 cited
Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor
2015· 1 cited
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Frequent Co-authors

Ding-Ming Kwai(40), Cheng‐Wen Wu(25), Chih-Yen Lo(9), Jin-Fu Li(8), Shi‐Yu Huang(8), Kuo-Liang Cheng(5), Chang‐Tzu Lin(5), Chih-Tsun Huang(4), Xuan-Lun Huang(4), Jiun-Lang Huang(4), Yun-Chao Yu(4), Yu-Hsiang Lin(3), Che-Wei Chou(3), Chih-Wea Wang(3), Jih‐Nung Lee(3), Rei-Fu Huang(3), Chih-Sheng Hou(3), Chia‐Hsin Lee(3), Ping-Ying Kang(3), Yung-Pin Lee(3)