P. Sivasubramani

The University of Texas at Dallas — United States

Engineering · Physical Sciences

14h-index741citations39works0.02yr avg
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Research Topics

Semiconductor materials and devices(37), Advancements in Semiconductor Devices and Circuit Design(17), Ferroelectric and Negative Capacitance Devices(13), Integrated Circuits and Semiconductor Failure Analysis(12), Electronic and Structural Properties of Oxides(8)

Publications39 total

Effects of growth temperature and oxidant feeding time on residual C- and N-related impurities and Si diffusion behavior in atomic-layer-deposited La2O3 thin films
Applied Surface Science·2013· 13 cited
Measurement of Schottky barrier height tuning using dielectric dipole insertion method at metal–semiconductor interfaces by photoelectron spectroscopy and electrical characterization techniques
Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena·2013· 17 cited
<i>In‐situ</i> X‐ray photoelectron spectroscopy of trimethyl aluminum and water half‐cycle treatments on HF‐treated and O<sub>3</sub>‐oxidized GaN substrates
physica status solidi (RRL) - Rapid Research Letters·2011· 24 cited
Impact of ozone concentration on atomic layer deposited HfO2 on GaAs
Microelectronic Engineering·2011· 2 cited
Reduction of Residual C and N-Related Impurities by Al2O3 Insertion in Atomic-Layer-Deposited La2O3 Thin Films
Electrochemical and Solid-State Letters·2011· 3 cited
Effects of O3 and H2O oxidants on C and N-related impurities in atomic-layer-deposited La2O3 films observed by <i>in situ</i> x-ray photoelectron spectroscopy
Applied Physics Letters·2010· 20 cited
Effect of Ozone Concentration on Atomic Layer Deposited HfO<sub>2</sub> on Si
ECS Transactions·2010· 3 cited
Effect of Ozone Concentration on Atomic Layer Deposited High-k Dielectric on Si and GaAs
ECS Meeting Abstracts·2010Open Access
Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning
ECS Transactions·2009
The Challenges in Introducing PMOS Dual Channel in CMOS Processing
ECS Transactions·2009
The Challenges in Introducing PMOS Dual Channel in CMOS Processing
ECS Meeting Abstracts·2009Open Access
La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application
2009· 2 cited
Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application
2008· 9 cited
The impact of la-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress conditions
2008· 14 cited
Effective surface passivation methodologies for high performance germanium metal oxide semiconductor field effect transistors
Applied Physics Letters·2008· 6 cited
Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT
2008· 15 cited
Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance
Proceedings of the International Power Modulator Symposium and High Voltage Workshop/Proceedings of the ... International Power Modulator Symposium and ... High Voltage Workshop·2008· 4 cited
Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs
2008· 2 cited
Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning
Applied Physics Letters·2008· 177 cited
Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond
2007· 6 cited
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Frequent Co-authors

Robert M. Wallace(17), P. D. Kirsch(14), R. Jammy(12), Bruce E. Gnade(12), Chadwin D. Young(11), G. Bersuker(11), Dawei Heh(9), H. R. Harris(8), P. Majhi(8), H.‐H. Tseng(8), Tae Joo Park(6), D. C. Gilmer(6), Manuel Quevedo-López(5), Muhammad M. Hussain(5), Daniel J. Lichtenwalner(5), Angus I. Kingon(5), J. Huang(5), Prashant Majhi(5), Jimin Huang(4), Rino Choi(4)