J. J. Bucchignano

IBM Research - Thomas J. Watson Research Center — United States

Engineering · Physical Sciences

18h-index1.2kcitations45works0.02yr avg
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Research Topics

Semiconductor materials and devices(28), Advancements in Semiconductor Devices and Circuit Design(20), Advancements in Photolithography Techniques(10), Integrated Circuits and Semiconductor Failure Analysis(8), Nanowire Synthesis and Applications(7)

Publications45 total

Intrinsically ultrastrong plasmon–exciton interactions in crystallized films of carbon nanotubes
Proceedings of the National Academy of Sciences·2018· 41 citedOpen Access
Intrinsically ultrastrong light-matter interactions in crystalline films of carbon nanotubes
arXiv (Cornell University)·2018· 1 citedOpen Access
200 mm wafer-scale integration of sub-20 nm sacrificial nanofluidic channels for manipulating and imaging single DNA molecules
2013· 4 cited
Graphene radio frequency devices on flexible substrate
Applied Physics Letters·2013· 48 cited
Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2013· 9 cited
Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly
Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena·2012· 33 cited
Patterning of CMOS device structures for 40-80nm pitches and beyond
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2012· 10 cited
A 0.021 µm 2 trigate SRAM cell with aggressively scaled gate and contact pitch
Symposium on VLSI Technology·2011· 8 cited
Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources
IEEE Electron Device Letters·2010· 59 cited
Effective Schottky Barrier lowering for contact resistivity reduction using silicides as diffusion sources
2010· 2 cited
High mobility III–V channel MOSFETs for post-Si CMOS applications
2009· 2 cited
High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and $\alpha$-Si Passivation
IEEE Electron Device Letters·2008· 107 cited
Scaling of In<inf>0.7</inf>Ga<inf>0.3</inf>As buried-channel MOSFETs
2008· 24 cited
High Performance Long-and Short-Channel In<inf>0.7</inf>Ga<inf>0.3</inf>As-channel MOSFETs
2008· 4 cited
Post-Si CMOS: III-V n-MOSFETs with high-k gate dielectrics
2007· 4 cited
Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes
Microelectronic Engineering·2006· 17 cited
Aggressively scaled (0.143 μm/sup 2/ ) 6T-SRAM cell for the 32 nm node and beyond
2005· 16 cited
Very high performance 50 nm CMOS at low temperature
2003· 5 cited
A high performance 0.25 mu m CMOS technology
2003· 26 cited
Two gates are better than one [double-gate MOSFET process]
IEEE Circuits and Devices Magazine·2003· 81 cited
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Frequent Co-authors

Shalom J. Wind(16), D. Klaus(11), Y. T. Lii(7), Michael Guillorn(7), F. J. Hohn(7), R. Viswanathan(7), C. Lavoie(6), J. Newbury(6), E. Kiewra(5), J. P. de Souza(5), Keith Fogel(5), P. M. Solomon(5), Yuan Taur(5), Phaedon Avouris(4), G. Shahidi(4), Y. J. Mii(4), M.G. Rosenfield(4), I. Babich(4), P. Kozlowski(4), R. Roy(4)