M. Rödder

Samsung (United States) — United States

Engineering · Physical Sciences

23h-index1.5kcitations109works0.02yr avg
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Research Topics

Semiconductor materials and devices(83), Advancements in Semiconductor Devices and Circuit Design(74), Silicon and Solar Cell Technologies(23), Integrated Circuits and Semiconductor Failure Analysis(21), Ferroelectric and Negative Capacitance Devices(20)

Publications109 total

A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out
2020· 17 cited
Integration of ALD high-k dipole layers into CMOS SOI nanowire FETs for bi-directional threshold voltage engineering
2020
SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications
2018· 123 cited
High-Accuracy Inference in Neuromorphic Circuits using Hardware-Aware Training
arXiv (Cornell University)·2018Open Access
High-Accuracy Inference in Neuromorphic Circuits using Hardware-Aware\n Training
arXiv (Cornell University)·2018Open Access
Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs
2018· 45 cited
Modeling of Negative Capacitance of Ferroelectric Capacitors as a Non-Quasi Static Effect
arXiv (Cornell University)·2018· 4 citedOpen Access
A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration
IEEE Journal of the Electron Devices Society·2018Open Access
A Multi-Bit Neuromorphic Weight Cell using Ferroelectric FETs, suitable\n for SoC Integration
arXiv (Cornell University)·2017Open Access
High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length
2017· 19 cited
Parasitic Bipolar Leakage in III-V FETs: Impact of Substrate Architecture
arXiv (Cornell University)·2017· 3 citedOpen Access
A crystalline oxide passivation on In0.53Ga0.47As (100)
Journal of Applied Physics·2017· 11 cited
A New Direction for III–V FETs for Mobile CPU Operation Including Burst-Mode: In<sub>0.35</sub>Ga<sub>0.65</sub>As Channel
IEEE Electron Device Letters·2017· 3 cited
バーストモードを含むモバイルCPU動作のためのIII‐V族FETのための新しい方向:In_0 35Ga_0Ga0.65Asチャネル【Powered by NICT】
IEEE Electron Device Letters·2017
A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond
2016· 30 cited
<i>In situ</i> surface and interface study of crystalline (3×1)-O on InAs
Applied Physics Letters·2016· 8 cited
Is electron transport in nanocrystalline Cu interconnects surface dominated or grain boundary dominated?
2016· 5 cited
Lower limits of line resistance in Back End of Line Cu interconnects
arXiv (Cornell University)·2016Open Access
Modulation of the Schottky Barrier Height for CMOS advanced contacts
Microelectronic Engineering·2016· 2 citedOpen Access
Modulation of the Schottky barrier height for advanced contact schemes
2015· 2 cited
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Frequent Co-authors

S. Aur(10), Amitava Chatterjee(9), S. V. Hattangady(9), J. A. Kittl(6), R. A. Chapman(6), Jerry C. Hu(6), Paul E. Nicollian(5), Titash Rakshit(4), A. Amerasekera(4), Antonio Rotondaro(4), D.T. Grider(4), D.A. Antoniadis(4), I.-C. Chen(4), M. Nandakumar(3), George Brown(3), Hsiwen Yang(3), D. Rogers(3), R. Kraft(3), Robert M. Wallace(3), Maureen A. Hanratty(3)