Daisuke Ryuzaki

Hitachi (Japan) — Japan

Materials Science · Physical Sciences

7h-index216citations33works0.02yr avg
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Research Topics

Copper Interconnects and Reliability(22), Semiconductor materials and devices(19), Advanced Surface Polishing Techniques(7), Advancements in Photolithography Techniques(4), Ultrasonics and Acoustic Wave Propagation(3)

Publications33 total

High-radiation Hardness 4H-SiC Transimpedance Amplifier featuring Stable Offset-voltage for Analog Sensors in Nuclear Power Plants
2020· 4 cited
A CMUT receiving probe with an integrated preamplifier for through-transmission scanning acoustic tomography
2020
Improvement in lateral resolution of through-transmission scanning acoustic tomography using capacitive micromachined ultrasound transducer
Microelectronics Reliability·2018· 7 cited
Through-Transmission Scanning Acoustic Tomography Using Capacitive Micromachined Ultrasound Transducer
2018· 3 cited
Plasma ion-beam 3D printing: A novel method for rapid fabrication of customized MEMS sensors
2018· 5 cited
Ultra-narrow gap CMUT cell structure for highly sensitive photoacoustic imaging
2017 IEEE International Ultrasonics Symposium (IUS)·2017· 3 cited
Cavity edge insulator extension in CMUT cell for high ultrasound power transmission
2017 IEEE International Ultrasonics Symposium (IUS)·2017· 1 cited
Design method for rapid customization of MEMS sensors
2017· 1 cited
Low-Shrinkage Spin-On Glass for Low Parasitic Capacitance Gap-Filling Process in Advanced Memory Devices
Japanese Journal of Applied Physics·2012· 1 cited
Chemical Mechanical Polishing with Nanocolloidal Ceria Slurry for Low-Damage Planarization of Dielectric Films
Japanese Journal of Applied Physics·2012· 1 cited
Low-Shrinkage Spin-On Glass for Low Parasitic Capacitance Gap-Filling Process in Advanced Memory Devices
Japanese Journal of Applied Physics·2012
Chemical Mechanical Polishing with Nanocolloidal Ceria Slurry for Low-Damage Planarization of Dielectric Films
Japanese Journal of Applied Physics·2012· 5 cited
Evaluation of Line-Edge Roughness in Cu/Low-k Interconnect Patterns
IEICE Technical Report; IEICE Tech. Rep.·2010
Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM
2009· 3 cited
Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern
Japanese Journal of Applied Physics·2008· 4 cited
Characterization of line-edge roughness in Cu/low- k interconnect pattern
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2007· 8 cited
Characterization of Line-edge Roughness in Cu/low-k Interconnect Pattern
2007· 6 cited
Scratch-free dielectric CMP slurry with 5-nm colloidal ceria abrasive
Symposium on VLSI Technology·2006
Thermally and Chemically Robust, Non-Reflowable Low-k Spin-on Glass (k = 2.4) for Gap-Filling Technology in Sub-50-nm Memory Devices
2006· 2 cited
Dual-Damascene Cu/Low-k Interconnect Fabrication Scheme Using Dissoluble Hard Mask Material
Journal of The Electrochemical Society·2006· 6 cited
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Frequent Co-authors

Ken’ichi Takeda(11), K. Hinode(8), Shuntaro Machida(8), Takeshi Furusawa(7), Haruaki Sakurai(7), Ryo Yoneyama(5), Atsuko Yamaguchi(5), Hiroki Kawada(5), Taiichi Takezaki(5), Toshiyuki Mine(4), Jiro Yamamoto(3), Takashi Iizumi(3), Masakazu Kawano(3), Yoichi Machii(3), Naoyuki Koyama(3), Toranosuke Ashizawa(3), Hiroaki HASEGAWA(3), Kazuyoshi Torii(3), Hiroshi Yamaguchi(2), Yoshio Homma(2)