R. Mann

GlobalFoundries (United States) — United States

Engineering · Physical Sciences

22h-index1.6kcitations58works0.02yr avg
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Research Topics

Semiconductor materials and devices(39), Advancements in Semiconductor Devices and Circuit Design(31), Semiconductor materials and interfaces(17), Low-power high-performance VLSI design(14), Integrated Circuits and Semiconductor Failure Analysis(10)

Publications58 total

Bias-Dependent Variation in FinFET SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2020· 7 cited
An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2019· 1 cited
Direct insight to SRAM array devices in advanced FinFET nodes by large scale ultra-fast in-situ characterization
2019· 1 cited
A Retrospective View on the Technology Evolution to Support Low Power Mobile Application
Journal of Low Power Electronics·2018
Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications
2017· 3 cited
Array Termination Impacts in Advanced SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2017· 4 cited
Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2016· 2 cited
Design and Performance Comparison of 6-T SRAM Cell in 32nm CMOS, FinFET and CNTFET Technologies
2016
Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing
2015· 3 cited
HTOL SRAM Vmin shift considerations in scaled HKMG technologies
2014· 3 cited
Advanced soft fail characterization methodology for sub-28nm nanoscale SRAM yield improvement
2014· 1 cited
High performance bulk planar 20nm CMOS technology for low power mobile applications
2012· 26 cited
Tracking On-Chip Age Using Distributed, Embedded Sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2011· 9 cited
Nonrandom Device Mismatch Considerations in Nanoscale SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems·2011· 16 cited
New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm
2011· 17 cited
Improving SRAM Vmin and yield by using variation-aware BTI stress
2010· 20 cited
Impact of circuit assist methods on margin and performance in 6T SRAM
Solid-State Electronics·2010· 50 cited
Limits of bias based assist methods in nano-scale 6T SRAM
2010· 18 cited
Sub-threshold circuit design with shrinking CMOS devices
2009· 61 cited
Optimization of DUV lithography for high-energy well implantation
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2007
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Frequent Co-authors

L. A. Clevenger(12), G. L. Miles(9), C. Cabral(8), Benton H. Calhoun(8), J. M. E. Harper(7), Terence B. Hook(7), Joseph Versaggi(6), D. Hoyniak(5), F. M. d’Heurle(5), P.E. Cottrell(5), R. Roy(5), K. L. Saenger(5), Jeffrey S. Brown(5), Junling Wang(5), Sheng Quan Xie(4), M. Weybright(3), J. Sudijono(3), M. Eller(3), James Nakos(3), Satyanand Nalam(3)