T. Sparks

Engineering · Physical Sciences

13h-index616citations53works0.02yr avg
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Research Topics

Semiconductor materials and devices(24), Copper Interconnects and Reliability(19), Plasma Diagnostics and Applications(11), Silicon and Solar Cell Technologies(10), Advancements in Semiconductor Devices and Circuit Design(8)

Publications53 total

Plasma Etch
2017
Device Level 3D Integration Technologies For High Performance/Reliability Modules
Pan Pacific Symposium·2011
22 nm technology compatible fully functional 0.1 μm<sup>2</sup> 6T-SRAM cell
2008· 32 cited
Plasma Etch
2007· 2 cited
Three dimensional chip stacking using a wafer-to-wafer integration
2007· 38 cited
A molecular dynamics investigation of fluorocarbon based layer-by-layer etching of silicon and SiO2
Journal of Applied Physics·2007· 87 cited
The Influence of Selected Material and Transport Parameters on the Accuracy of Modeling Early Voltage in SiGe-Base HBT
2006
Salinity Investment Framework, Phase II
2006· 11 cited
Electrical Distribution System Management
1990 IEEE Nuclear Science Symposium Conference Record·2005
SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells
2005· 19 cited
Integration challenges of 0.1 μm CMOS Cu/low-k interconnects
2003· 4 cited
Integration of SiCN as a low κ etch stop and Cu passivation in a high performance Cu/low κ interconnect
2003· 12 cited
Model for magnetically enhanced capacitively coupled plasma discharges
2003
Integrated equipment-feature modeling investigation of fluorocarbon plasma etching of SiO2 and photoresist
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena·2003· 18 cited
A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations
2003· 4 cited
Introduction of BiCMOS into a production CMOS facility
2002· 4 cited
Introduction of BiCMOS into a production CMOS facility
2002· 1 cited
A high performance 1.5 V, 0.10 μm gate length CMOS technology with scaled copper metallization
2002· 12 cited
Integration of multi-level copper metallization into a high performance sub-0.25 μm CMOS technology
2002
A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization
2002· 101 cited
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Frequent Co-authors

Simon Karecki(10), R. Reif(10), Victor Vartanian(10), Ritwik Chatterjee(9), R. A. Pryor(9), S. Filipiak(8), Laura Pruette(8), M. G. Coleman(8), P. Crabtree(7), J. Farkas(7), Laurie Beu(7), D. Denning(7), T. Stephens(7), S. Venkatesan(6), E. Weitzman(6), Shahid Rauf(6), Peter L. G. Ventzek(6), K. Junker(6), M. Herrick(5), T. Lii(5)