T. Lii

Texas Instruments (United States) — United States

Engineering · Physical Sciences

9h-index377citations35works0.02yr avg
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Research Topics

Semiconductor materials and devices(24), Advancements in Semiconductor Devices and Circuit Design(13), Copper Interconnects and Reliability(11), Integrated Circuits and Semiconductor Failure Analysis(8), Metal and Thin Film Mechanics(5)

Publications35 total

Controlling Asymmetric Photoresist Feature Dimensions during Plasma-Assisted Shrink
Plasma Processes and Polymers·2014
Selective etching of TiN over TaN and vice versa in chlorine-containing plasmas
Journal of Vacuum Science & Technology A Vacuum Surfaces and Films·2013· 10 cited
Differences in erosion mechanism and selectivity between Ti and TiN in fluorocarbon plasmas for dielectric etch
Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena·2012· 6 cited
Study of Ti etching and selectivity mechanism in fluorocarbon plasmas for dielectric etch
Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena·2012· 7 cited
Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2007· 3 cited
Transition from precise to accurate critical dimension metrology
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2007· 4 cited
The Influence of Selected Material and Transport Parameters on the Accuracy of Modeling Early Voltage in SiGe-Base HBT
2006
THE FLUCTUATING ASYMMETRY OF SOME MORPHOMETRIC CHARACTERS OF THE SKULL IN A POPULATION OF MUS SPICIL EGUS, PETENY, 1882 (MAMMALIA: RODENTIA) FROM A CROP OF WHEAT IN THE COUNTY OF BOTOŞANI
2006
Integration challenges of 0.1 μm CMOS Cu/low-k interconnects
2003· 4 cited
A novel borderless contact/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic
2002· 6 cited
Trench storage capacitors for high density DRAMs
2002· 9 cited
Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing
2002· 32 cited
Dry etch sequencing induced gate oxide degradation due to metallic contamination in 0.25 μm CMOS manufacturing
2002
Integration of multi-level copper metallization into a high performance sub-0.25 μm CMOS technology
2002
A manufacturable and modular 0.25 μm CMOS platform technology
2002· 3 cited
A high performance 3.97 μm/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization
2002· 7 cited
Optimization of a 0.18 μm 1.5 V CMOS technology to achieve 15 ps gate delay
2002· 3 cited
A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization
2002· 101 cited
High performance 0.25 μm SRAM technology with tungsten interpoly plug
2002· 4 cited
A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications
2002· 18 cited
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Frequent Co-authors

P. Gilbert(6), S. Venkatesan(5), T. Sparks(5), A.H. Perera(5), P. Crabtree(4), J. Farkas(4), S. Filipiak(4), Yuan Taur(4), D. Quinlan(4), D. Denning(4), M. Woo(4), Veena Misra(4), C. Capasso(3), K. Reid(3), C. Simpson(3), Pik Fong Tsui(3), D. Watts(3), E. Weitzman(3), Y. J. Mii(3), D. A. Danner(3)