Pranay Prabhat

ARM (United Kingdom) — United Kingdom

Engineering · Physical Sciences

9h-index490citations20works0.02yr avg
OpenAlex↗ORCID↗Google Scholar↗Lab page↗

Accepting Students?

No reports yet. Know if this professor is taking students?

Research Topics

Low-power high-performance VLSI design(15), Analog and Mixed-Signal Circuit Design(10), Advancements in Semiconductor Devices and Circuit Design(7), Advanced Memory and Neural Computing(6), Parallel Computing and Optimization Techniques(3)

Publications20 total

A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits
Journal of Low Power Electronics and Applications·2022Open Access
Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems·2022· 9 cited
A Fokker-Planck Solver to Model MTJ Stochasticity
2021· 1 citedOpen Access
A Compact Model for Scalable MTJ Simulation
arXiv (Cornell University)·2021· 1 citedOpen Access
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller
IEEE Journal of Solid-State Circuits·2020· 13 cited
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power
2020· 27 cited
A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing
2019· 5 cited
A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation <i>RC</i> Oscillator With Forward-Body-Biasing
IEEE Solid-State Circuits Letters·2019· 5 cited
A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V V<sub>min</sub> and 47fJ/b access energy
2019· 2 cited
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup
2018· 4 cited
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
IEEE Journal of Solid-State Circuits·2018· 98 cited
Dataset for 'Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS'
ePrints Soton (University of Southampton)·2018Open Access
Evaluation and analysis of single-phase clock flip-flops for NTV applications
2017· 4 cited
Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library
2017· 15 cited
A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks
2017· 32 cited
Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem
2016· 2 cited
A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator
IEEE Journal of Solid-State Circuits·2015· 86 cited
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0&amp;#x002B; subsystem in 65nm CMOS for WSN applications
2015· 74 cited
Low power memory implementation for a GHz&amp;#x002B; Dual Core ARM Cortex A9 processor on a high-K metal gate 32nm low power process
2011· 5 cited
Biomedical instrumentation based on electrooculogram (eog) signal processing and application to a hospital alarm system
2005· 107 cited

Frequent Co-authors

James Myers(15), Anand Savanth(10), Alex S. Weddell(4), Rohan Gaddh(4), Benoît Labbe(4), Graham Knight(4), Philex Ming-Yan Fan(4), Yunpeng Cai(3), David Flynn(3), Sheng Yang(3), Supreet Jeloka(3), Fernando Garćıa-Redondo(3), Tom J. Kázmierski(2), David Howard(2), Thanusree Achuthan(2), Jordan Morris(2), Alex Yakovlev(2), Mudit Bhargava(2), Shashanka Venkataramanan(1), S.R. Choudhury(1)