B. Tavel

Soitec (France) — France

Engineering · Physical Sciences

11h-index484citations31works0.02yr avg
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Research Topics

Semiconductor materials and devices(23), Advancements in Semiconductor Devices and Circuit Design(21), Integrated Circuits and Semiconductor Failure Analysis(6), Advanced Memory and Neural Computing(4), Advancements in Photolithography Techniques(4)

Publications31 total

A Single Smart Cut POI Substrate Design for UHF, L and S Band Filters
2021· 10 cited
Innovative Smart Cut™ Piezo On Insulator (POI) Substrates for 5G acoustic filters
2020· 61 cited
Smart Cut™ Piezo On Insulator (POI) substrates for high performances SAW components
2020· 52 cited
New generation of composite substrates based on a layer of LiTaO3 on silicon for surface acoustic waves components
HAL (Le Centre pour la Communication Scientifique Directe)·2020· 2 citedOpen Access
Surface Preparation Challenge on Nitrided Gate Oxides
Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena·2007Open Access
Surface Preparation Challenge on Nitrided Gate Oxides
Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena·2007
Gate Oxide Cleans on Single Wafer Tool
ECS Transactions·2007· 6 cited
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
Solid-State Electronics·2006· 2 cited
MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
2005· 8 cited
0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications
2005· 14 cited
New hole trapping characterization during NBTI in 65nm node technology with distinct nitridation processing
2005· 9 cited
Poly-gate replacement through contact hole (PRETCH): a new method for high-K/metal gate and multi-oxide implementation on chip
2005· 12 cited
65nm LP/GP mix low cost platform for multi-media wireless and consumer applications
2005· 11 cited
Low temperature process flow optimisation for 65nm CMOS mixed-signal applications
2004· 1 cited
65 nm Device Manufacture Using Shaped E-Beam Lithography
Japanese Journal of Applied Physics·2004· 9 cited
Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2004· 4 cited
Towards a better EOT - mobility trade-off in high-k oxide/metal gate CMOS devices
2004· 5 cited
Thin oxynitride solution for digital and mixed-signal 65nm CMOS platform
2004· 18 cited
New concept of high-k integration in MOSFET’s by a deposition through contact holes
Microelectronic Engineering·2004
Gate Dielectric Impact for the 65nm Digital and Mixed Signal Platform Applications
2004· 1 cited
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Frequent Co-authors

F. Arnaud(12), T. Skotnicki(11), P.A. Stolk(11), D. Barge(10), B. Duriez(8), M. Bidaud(7), M. Denais(7), K. Rochereau(7), R. Difrenza(7), F. Leverd(6), F. Bœuf(6), Y. Laplanche(6), M. Broekaart(6), M. Woo(6), C. Julien(5), Alessio Beverina(5), N. Planes(5), P. Gouraud(5), J. Biénacel(5), Philippe Garnier(5)