Eric Chang

United States Department of Veterans Affairs — United States

Engineering · Physical Sciences

15h-index667citations40works0.02yr avg
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Research Topics

Photonic and Optical Devices(13), Radio Frequency Integrated Circuit Design(9), Optical Network Technologies(9), Low-power high-performance VLSI design(7), Advanced Photonic Communication Systems(7)

Publications40 total

An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET
IEEE Journal of Solid-State Circuits·2021· 19 cited
An Automated and Process-Portable Generator for Phase-Locked Loop
2021· 6 cited
Weakly Supervised Contrastive Learning for Chest X-Ray Report Generation
arXiv (Cornell University)·2021Open Access
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET
2021· 13 cited
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies
IEEE Transactions on Circuits and Systems I Regular Papers·2021· 29 cited
Weakly Supervised Contrastive Learning for Chest X-Ray Report Generation
2021· 55 citedOpen Access
Design and Automatic Generation of High-Speed Circuits for Wireline Communications
2019
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance
IEEE Journal of Solid-State Circuits·2019· 22 cited
BAG: A Process-Portable Framework for Generator-based AMS Circuit Design
2019· 29 cited
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET
2019· 6 cited
An Automated SerDes Frontend Generator Verified With a 16-nm Instance Achieving 15 Gb/s at 1.96 pJ/bit
IEEE Solid-State Circuits Letters·2018· 8 cited
A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET
2018· 7 cited
An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit
2018· 4 cited
BAG2: A process-portable framework for generator-based AMS circuit design
2018· 118 cited
A 65-nm CMOS $I/Q$ RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering
IEEE Journal of Solid-State Circuits·2018· 15 cited
A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET
2017· 8 cited
A 65nm CMOS I/Q RF power DAC with 24–42dB 3<sup>rd</sup> harmonic cancellation and up to 18dB mixed-signal filtering
2017· 1 cited
Drain-Extended FinFET Technology for RF Power Applications
Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials·2016
Microring-based multi-chip WDM photonic module
Optics Express·2015· 12 citedOpen Access
An all-solid-state, WDM silicon photonic digital link for chip-to-chip communications
Optics Express·2015· 18 citedOpen Access
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Frequent Co-authors

Elad Alon(15), Jon Lexau(12), Borivoje Nikolić(11), Philip Amberg(11), Ivan Shubin(11), Ron Ho(11), J. E. Cunningham(11), Ashok V. Krishnamoorthy(11), Xuezhe Zheng(10), Hiren Thacker(10), Jaeduk Han(9), Frankie Liu(9), Nathan Narevsky(8), Kannan Raj(8), Woorham Bae(7), Ying Luo(7), Jin Yao(7), Jin-Hyoung Lee(6), Zhongkai Wang(5), Stevan S. Djordjevic(5)