King-Jien Chui

Agency for Science, Technology and Research — Singapore

Engineering · Physical Sciences

11h-index482citations41works3.52yr avg
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Research Topics

Semiconductor materials and devices(23), 3D IC and TSV technologies(21), Advancements in Semiconductor Devices and Circuit Design(14), Electronic Packaging and Soldering Technologies(11), Nanowire Synthesis and Applications(6)

Publications41 total

Design and Fabrication of 2.5D Cryogenic Interposer With Integrated Superconducting TSVs and Resonators
2024· 2 cited
Electrical Characterization and Reliability Studies of Nano-TSV
2024· 5 cited
Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications
2023· 5 cited
Investigation of SnAg Superconductivity as Solder Material for Cryogenic Packaging
2023· 1 cited
Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration
2023· 5 cited
Indium-based Flip-chip Interconnect for Cryogenic Packaging
2023· 1 cited
Room Temperature Plasma-Enhanced Niobium-Niobium Wafer Bonding for 3D Integration of Superconducting Interconnects for Quantum Processing
2023· 2 cited
Demonstration and Challenges of Through Si Interposer (TSI) with 5-layer Frontside Cu Metal and 2-layer Backside Cu RDL
2023· 1 cited
CMOS-Compatible Fine Pitch Al-Al Bonding
2023· 9 cited
A Precise Wafer Thinning Integration Process for nano-TSV Formation
2023· 4 cited
Demonstration of a CMOS-Compatible Superconducting Cryogenic Interposer for Advanced Quantum Processors
2023· 9 cited
Wafer Stacked Wide I/O DRAM with One-step TSV Technology
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)·2022· 5 cited
3D Cryogenic Interposer for Quantum Computing Application
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)·2022· 9 cited
Cu CMP Dishing in High Density Cu Pad for Fine Pitch Wafer-to-Wafer (W2W) Hybrid Bonding
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)·2021· 15 cited
One-step TSV process development for 4-layer wafer stacked DRAM
2021· 5 cited
Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials
2020· 10 cited
Temporary Bonding and De-bonding Process for 2.5D/3D Applications
2020· 12 cited
Wafer Level High Density Hybrid Bonding for High Performance Computing
2020· 16 cited
A 2-tier Embedded 3D Capacitor with High Aspect Ratio TSV
2020· 3 cited
Under-Bump Metallization Contact Resistance ( $R_{c}$ ) Characterization at 10- $\mu \text{m}$ Polymer Passivation Opening
IEEE Transactions on Components Packaging and Manufacturing Technology·2017· 7 cited
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Frequent Co-authors

Yee‐Chia Yeo(14), Kah‐Wee Ang(13), Ganesh S. Samudra(12), Chih-Hang Tung(10), Hongyu Li(9), Mingfu Li(7), N. Balasubramanian(7), Qin Ren(5), Woon Leng Loh(5), Chit Siong Lau(5), Narayanan Balasubramanian(4), Kuan Eng Johnson Goh(4), Norhanani Jaafar(4), Simon Chun Kiat Goh(4), Lai-Yin Wong(3), Ganesh Samudra(3), A. O. Adeyeye(3), Masaya Kawano(3), Anuj Madan(3), Mingbin Yu(3)