A. Murthy

Solamalai College of Engineering

Engineering · Physical Sciences

18h-index3.7kcitations24works0.02yr avg
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Research Topics

Semiconductor materials and devices(19), Advancements in Semiconductor Devices and Circuit Design(19), Nanowire Synthesis and Applications(5), Integrated Circuits and Semiconductor Failure Analysis(5), Silicon Carbide Semiconductor Technologies(4)

Publications24 total

Multi Objective Optimization for Crashworthiness Parameters of Thin Walled Tubes with Optimal Alkali Treated Coir/Polyester Filled in Axial Quasi Static Loading Using Grey Relation Analysis and ANNOVA
Springer Proceedings in Materials·2024
Gate-All-Around Strained Si<sub>0.4</sub>Ge<sub>0.6</sub> Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application
2020· 46 cited
Analysis and Performance Comparison of CMOS and FinFET based DRAM Memory Cell
2016
The Seventeen And Nineteen Level Asymmetrical Cascaded H-Bridge MLI With Minimum Number Of Switches As Their Input Of Photovoltaic Arrays With Grid Connection
2013
(Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling
ECS Transactions·2010· 75 cited
Past, Present and Future: SiGe and CMOS Transistor Scaling
ECS Meeting Abstracts·2010· 28 citedOpen Access
Improvement in Noise Transmission Across Firewall of a Passenger Car
SAE technical papers on CD-ROM/SAE technical paper series·2010· 5 cited
High performance 32nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt; generation high-k + metal gate transistors
2009· 184 cited
Session 16: Process technology - Ge-Channel CMOS and advanced gate stacks
2008
A 32nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt;-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&amp;#x03BC;m&lt;sup&gt;2&lt;/sup&gt; SRAM cell size in a 291Mb array
2008· 184 cited
High performance Hi-K + metal gate strain enhanced transistors on (110) silicon
2008· 57 cited
Process Technology - Advanced Junctions, Silicides and Novel Stress Engineering
2007
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell
2005· 230 cited
A 90-nm logic technology featuring strained-silicon
IEEE Transactions on Electron Devices·2004· 654 cited
A Logic Nanotechnology Featuring Strained-Silicon
IEEE Electron Device Letters·2004· 511 cited
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
2004· 559 cited
Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology
2004· 153 cited
A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 μm/sup 2/ 6-T SRAM cell
2003· 30 cited
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell
2003· 241 cited
High performance fully-depleted tri-gate CMOS transistors
IEEE Electron Device Letters·2003· 453 cited
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Frequent Co-authors

R. Chau(8), T. Ghani(8), M Armstrong(7), S. Sivakumar(7), J. Kavalieros(7), C. Auth(6), S. Cea(6), C. Kenyon(6), M. Bohr(6), Scott E. Thompson(5), Kelin J. Kuhn(5), K. Mistry(5), M. Doczy(5), C. Weber(5), Reza Arghavani(5), G. Glass(4), J. W. Klaus(4), B. McIntyre(4), R. Shaheed(4), P. Packan(4)