P. Packan

Intel (United States) — United States

Engineering · Physical Sciences

27h-index2.7kcitations48works5.02yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(33), Semiconductor materials and devices(32), Integrated Circuits and Semiconductor Failure Analysis(13), Silicon and Solar Cell Technologies(12), Silicon Carbide Semiconductor Technologies(5)

Publications48 total

An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications
2024· 5 cited
Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
2023· 59 cited
Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 40 cited
High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology
2015· 49 cited
Transistor aging and reliability in 14nm tri-gate technology
2015· 65 cited
A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size
2014· 522 cited
Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures
2014· 45 cited
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
2013· 84 cited
Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology
2010· 59 cited
High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors
2009· 184 cited
A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array
2008· 184 cited
High performance Hi-K + metal gate strain enhanced transistors on (110) silicon
2008· 57 cited
Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs
IEEE Transactions on Electron Devices·2006· 21 cited
Halo Doping: Physical Effects and Compact Modeling
TechConnect Briefs·2006· 3 cited
Introductory Remarks: Process Development and Modeling
ECS Transactions·2006
A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors
2006· 43 cited
An efficient surface potential solution algorithm for compact MOSFET models
2005· 33 cited
Predictive compact modeling of HQS effects and thermal noise in 90nm mixed signal/RF CMOS technology
2005· 10 cited
A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications
2004· 67 cited
A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 μm/sup 2/ 6-T SRAM cell
2003· 30 cited
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Frequent Co-authors

T. Ghani(13), M. Bohr(10), S. Natarajan(9), K. Mistry(8), M.D. Giles(7), Scott E. Thompson(7), I. Post(7), S. Mudanai(7), R. Rios(6), Harold Kennel(6), M. Agostinelli(5), B. Sell(5), S. Sivakumar(5), S. Tyagi(5), C. Prasad(5), Kelin J. Kuhn(5), C. Kenyon(4), Ayushi Paliwal(4), C. Parker(4), Leonard C. Pipes(4)