C. Parker

Jacksonville College — United States

Engineering · Physical Sciences

8h-index1.6kcitations17works0.52yr avg
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Research Topics

Semiconductor materials and devices(11), Advancements in Semiconductor Devices and Circuit Design(11), Ferroelectric and Negative Capacitance Devices(4), Analog and Mixed-Signal Circuit Design(2), Integrated Circuits and Semiconductor Failure Analysis(2)

Publications17 total

69-Year-Old Man With Acute Kidney Injury
Mayo Clinic Proceedings·2025· 1 cited
HIGH-GRADE B-CELL LYMPHOMA CAUSING ACUTE CARDIAC TAMPONADE
Journal of the American College of Cardiology·2024
Impact of Professional Society Guideline Publications in Medicine Subspecialties From 2012 to 2022: Implications for Clinical Care and Health Policy
Mayo Clinic Proceedings Innovations Quality & Outcomes·2023· 2 citedOpen Access
DASATINIB-INDUCED CARDIAC TAMPONADE PRIOR TO HEMATOPOIETIC STEM CELL TRANSPLANT
Journal of the American College of Cardiology·2022· 1 cited
A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2017· 354 cited
Transistor aging and reliability in 14nm tri-gate technology
2015· 65 cited
A 14nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt;-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &amp;#x00B5;m&lt;sup&gt;2&lt;/sup&gt; SRAM cell size
2014· 522 cited
Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology
2012· 18 cited
High performance 32nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt; generation high-k + metal gate transistors
2009· 184 cited
A 32nm logic technology featuring 2&lt;sup&gt;nd&lt;/sup&gt;-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&amp;#x03BC;m&lt;sup&gt;2&lt;/sup&gt; SRAM cell size in a 291Mb array
2008· 184 cited
LowTemperature Performance ofDeepSubmicron Germanium pMOSFETs
2007
Multiple Independent Gate Field Effect Transistors Device, Process, Applications
2006
Multiple Independent Gate Field Effect Transistors Device, Process, Applications
ECS Meeting Abstracts·2006· 4 citedOpen Access
Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors
2006· 33 cited
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell
2005· 230 cited
Measurement based multi-port models for HSS link channel coupling
Electrical Performance of Electronic Packaging·2005
Multi gated device architectures advances, advantages and challenges
2004· 5 cited

Frequent Co-authors

S. Natarajan(5), R. Heussner(5), V. Chikarmane(4), R. James(4), C. Kenyon(4), Miao Liu(4), P. Packan(4), Leonard C. Pipes(4), S. Sivakumar(4), L. Mathew(4), T. Stephens(4), M. Bost(3), T. Ghani(3), Ik Kyeong Jin(3), L. Neiberg(3), C. Pelto(3), K. Tone(3), T. Troeger(3), Kedong Zhang(3), G. Ding(3)