I. Post

Intel (United States) — United States

Engineering · Physical Sciences

17h-index2.0kcitations35works0.02yr avg
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Research Topics

Semiconductor materials and devices(26), Advancements in Semiconductor Devices and Circuit Design(23), Radio Frequency Integrated Circuit Design(6), Silicon Carbide Semiconductor Technologies(5), Silicon Nanostructures and Photoluminescence(5)

Publications35 total

A Reliability Overview of Intel’s 10+ Logic Technology
2020· 13 cited
Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing
2018· 34 cited
A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2017· 354 cited
Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures
2014· 45 cited
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
2013· 84 cited
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
2012· 749 cited
Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology
2010· 6 cited
A 32nm SoC platform technology with 2&lt;sup&gt;nd&lt;/sup&gt; generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
2009· 75 cited
Future device scaling - Beyond traditional CMOS
2009· 1 cited
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
2008· 45 cited
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications
2007· 31 cited
A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors
2006· 43 cited
A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications
2006· 57 cited
A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications
2004· 67 cited
A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 μm/sup 2/ 6-T SRAM cell
2003· 30 cited
ACUTE: a high performance analog complementary polysilicon emitter bipolar technology utilizing SOI/trench full dielectric isolation
2002· 7 cited
Poly-crystalline silicon-carbide (SiCarb) emitter bipolar transistors
2002
Modeling and characterization of noise of polysilicon emitter bipolar transistors
2002· 8 cited
A high performance 180 nm generation logic technology
2002· 89 cited
Source/drain extension scaling for 0.1 μm and below channel length MOSFETs
2002· 50 cited
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Frequent Co-authors

P. Ashburn(15), C. Auth(7), P. Packan(7), Z.A. Shafi(7), K. Mistry(6), Peng Bai(6), Markus J. Buehler(5), J. Hicks(5), S. Ramey(5), C. Tsai(5), C.-H. Jan(5), W. Hafez(5), Jiefeng Lin(5), Kelin J. Kuhn(5), T. Ghani(4), M. Hattendorf(4), M. B. Prince(4), M. Bohr(4), C. Prasad(4), M. Agostinelli(4)