M. Hattendorf

Intel (United States) — United States

Engineering · Physical Sciences

14h-index2.8kcitations30works5.02yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(17), Semiconductor materials and devices(15), Radio Frequency Integrated Circuit Design(6), Semiconductor Lasers and Optical Devices(6), Semiconductor Quantum Structures and Devices(4)

Publications30 total

Intel 18A Platform Technology Featuring RibbonFET (GAA) and PowerVia for Advanced High-Performance Computing
2025· 5 cited
An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications
2024· 5 cited
Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 40 cited
A Reliability Overview of Intel’s 10+ Logic Technology
2020· 13 cited
A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2017· 354 cited
Intrinsic transistor reliability improvements from 22nm tri-gate technology
2013· 166 cited
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
2012· 749 cited
Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology
IEEE International Reliability Physics Symposium proceedings·2009· 13 cited
High performance Hi-K + metal gate strain enhanced transistors on (110) silicon
2008· 57 cited
45nm High-k + metal gate strain-enhanced transistors
2008· 204 cited
Dielectric breakdown in a 45 nm high-k/metal gate process technology
2008· 26 cited
BTI reliability of 45 nm high-K + metal-gate process technology
2008· 130 cited
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
2007· 825 cited
A 45nmLogicTechnology withHigh-k+Metal GateTransistors, Strained Silicon, 9CuInterconnect Layers, 193nmDryPatterning, and100%Pb-free Packaging
2007
A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications
2004· 67 cited
W-band InGaP/GaAs HBT MMIC frequency sources
2003· 3 cited
Impact of 1/f noise in Ka-band InGaP/GaAs HBT frequency sources
2002· 3 cited
Submicron Scaling in Indium Phosphide/indium Gallium Arsenide Single Heterojunction Bipolar Transistors
2002
Reliability Study of Low-Voltage RF MEMS Switches
2002· 25 cited
Sub-micron Scaling of High-Speed InP/InGaAs SHBTs Grown by MOCVD using Carbon as the p-Type Dopant
2002· 7 cited
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Frequent Co-authors

C. Auth(10), K. Mistry(9), T. Ghani(9), M. Feng(9), J. Hicks(8), J. Sandford(8), Kelin J. Kuhn(7), Markus J. Buehler(6), S. Jaloviar(6), C. Prasad(6), J. Maiz(5), Sangwoo Pae(5), Leonard C. Pipes(5), M. B. Prince(5), D. Bergstrom(5), Christopher W. Thomas(5), T. Troeger(5), M. Brazier(5), S. Ramey(5), D.A. Ahmari(5)