B. Jagannathan

Engineering · Physical Sciences

27h-index2.5kcitations81works2.02yr avg
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Research Topics

Radio Frequency Integrated Circuit Design(49), Semiconductor materials and devices(32), Advancements in Semiconductor Devices and Circuit Design(28), Silicon and Solar Cell Technologies(17), Thin-Film Transistor Technologies(15)

Publications81 total

Automated and flexible optical and RF test and measurement methodology for CMOS-compatible 300mm silicon photonics technologies
2026
SILAR deposited Cu2MnSnS4 thin films for sustainable energy applications
Materials Letters·2024· 4 cited
A 7nm CMOS technology platform for mobile and high performance compute application
2017· 58 cited
High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization
2014· 128 cited
22nm technology yield optimization using multivariate 3D virtual fabrication
2013· 4 cited
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
2012· 89 cited
Leakage Engineering Enabling PDSOI Ring Oscillators Operating in Sub-100pA/µm I<sub>off</sub> Regime
ECS Transactions·2011
Extremely-Thin SOI for Mainstream CMOS: Challenges and Opportunities
2010
Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices
IEEE Journal of Solid-State Circuits·2010· 18 cited
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
2010· 39 cited
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
2010· 28 cited
A 150 GHz Amplifier With 8 dB Gain and $+$6 dBm $P_{\rm sat}$ in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines
IEEE Journal of Solid-State Circuits·2009· 68 cited
Effect of substrate contact shape and placement on RF characteristics of 45 nm low power CMOS devices
2009· 9 citedOpen Access
RF Modeling of 45nm Low-Power CMOS Technology
TechConnect Briefs·2009· 2 cited
A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip lines
2009· 55 cited
Record RF performance of 45-nm SOI CMOS Technology
2007· 179 cited
SOI CMOS Technology with 360GHz f&lt;inf&gt;T&lt;/inf&gt; NFET, 260GHz f&lt;inf&gt;T&lt;/inf&gt; PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog System-on-Chip Applications
2007· 25 cited
Technology Scaling and Device Design for 350 GHz RF Performance in a 45nm Bulk CMOS Process
2007· 47 cited
Experimental analysis of on-wafer de-embedding techniques for RF modeling of advanced RFCMOS and BiCMOS technologies
2007· 2 cited
RF characterization and parameter extraction for CMOS device models
2007· 4 cited
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Frequent Co-authors

G. Freeman(24), D. Ahlgren(18), D. Greenberg(17), Jae-Sung Rieh(16), S. Subbanna(15), K. Schonenberg(11), K. Stein(11), John J. Pekarik(10), R. Groves(9), S.J. Jeng(9), Alvin Joseph(9), J. Johnson(8), Andy Stricker(7), G. Freeman(7), Susan L. Sweeney(7), C.M. Schnabel(6), Marwan Khater(6), L. Wagner(6), D.L. Harame(6), F. Pagette(5)