Nikola Nedovic

Nvidia (United States) — United States

Engineering · Physical Sciences

20h-index1.1kcitations49works2.02yr avg
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Research Topics

Low-power high-performance VLSI design(20), Advancements in PLL and VCO Technologies(18), Semiconductor Lasers and Optical Devices(14), Photonic and Optical Devices(11), Radio Frequency Integrated Circuit Design(10)

Publications49 total

Carrier Photogeneration Impact on Ring Dynamics
2025
A Roadmap Toward Sub 1pJ/b Optical Interconnect
2025
Optical Interchannel Interference in Dense Wavelength Division Multiplexing Systems
2024
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking
2024· 8 cited
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
IEEE Journal of Solid-State Circuits·2023· 9 cited
A microring resonator-based clock-forwarded DWDM optical interconnect in a monolithic silicon photonics process
IET conference proceedings.·2023· 3 cited
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
2023· 9 cited
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
IEEE Journal of Solid-State Circuits·2023· 45 cited
Methodology for Device, Circuit and Architecture Level Co-design and Optimization of Dense Wavelength Division Multiplexing Links
2023· 3 cited
Beyond CPO: A Motivation and Approach for Bringing Optics Onto the Silicon Interposer
Journal of Lightwave Technology·2022· 48 cited
Clock and Timing in Wireline Communications
River Publishers eBooks·2022
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 13 cited
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 13 cited
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links
2020· 5 cited
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
2019· 51 cited
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET
2019· 1 cited
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET
2019· 10 cited
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
IEEE Journal of Solid-State Circuits·2018· 61 cited
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects
2018· 28 cited
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator
2018· 42 cited
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Frequent Co-authors

Vojin G. Oklobdzija(21), C. Thomas Gray(16), Brian Zimmer(13), Sanquan Song(13), Stephen G. Tell(13), John W. Poulton(10), John Wilson(9), Walker J. Turner(9), William J. Dally(9), William W. Walker(9), Xi Chen(7), Sudhir S. Kudva(6), Hirotaka Tamura(6), M. Aleksić(5), N. Tzartzanis(5), Vladimir Stojanović(4), Dejan Marković(4), Angad Rekhi(4), Thomas H. Greer(4), Yoshinori Nishi(4)