Stephen G. Tell

Nvidia (United States) — United States

Engineering · Physical Sciences

17h-index1.4kcitations43works2.82yr avg
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Research Topics

Advancements in PLL and VCO Technologies(13), Semiconductor Lasers and Optical Devices(10), 3D IC and TSV technologies(9), Radio Frequency Integrated Circuit Design(8), Low-power high-performance VLSI design(8)

Publications43 total

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm
IEEE Journal of Solid-State Circuits·2026
A 77 fJ/Bit 8 Gbps Low-Latency Self-Timed Die-to-Die Link for 2.5D and 3D Interconnect in 3nm
2025· 1 cited
17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process
2025· 2 cited
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking
2024· 8 cited
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
IEEE Journal of Solid-State Circuits·2023· 9 cited
A microring resonator-based clock-forwarded DWDM optical interconnect in a monolithic silicon photonics process
IET conference proceedings.·2023· 3 cited
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
2023· 9 cited
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
IEEE Journal of Solid-State Circuits·2023· 44 cited
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
IEEE Journal of Solid-State Circuits·2023· 45 cited
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop
IEEE Journal of Solid-State Circuits·2022· 10 cited
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 13 cited
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 13 cited
A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 40 cited
A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)·2021· 4 cited
Simba
Communications of the ACM·2021· 19 citedOpen Access
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links
2020· 5 cited
A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
IEEE Journal of Solid-State Circuits·2020· 106 cited
Simba
2019· 365 cited
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology
2019· 13 cited
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
2019· 52 cited
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Frequent Co-authors

C. Thomas Gray(28), Brian Zimmer(24), William J. Dally(22), John W. Poulton(17), Sanquan Song(13), Nikola Nedovic(13), John Wilson(11), Walker J. Turner(11), Matthew Fojtik(9), Xi Chen(9), Ben Keller(8), Brucek Khailany(8), Rangharajan Venkatesan(7), Raj K. Singh(7), Sudhir S. Kudva(7), Alicia Klinefelter(6), Nathaniel Pinckney(6), Thomas H. Greer(6), Yakun Sophia Shao(5), Priyanka Raina(5)