Brian Zimmer

Nvidia (United States) — United States

Engineering · Physical Sciences

21h-index1.7kcitations59works3.22yr avg
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Research Topics

Low-power high-performance VLSI design(21), Parallel Computing and Optimization Techniques(14), Advanced Neural Network Applications(12), Semiconductor materials and devices(9), Advancements in Semiconductor Devices and Circuit Design(9)

Publications59 total

A 77-fJ/bit 8-Gbps Adaptive-Voltage-Compatible Self-Timed Die-to-Die Link for 2.5-D and 3-D Interconnect in 3 nm
IEEE Journal of Solid-State Circuits·2026
A 77 fJ/Bit 8 Gbps Low-Latency Self-Timed Die-to-Die Link for 2.5D and 3D Interconnect in 3nm
2025· 1 cited
17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process
2025· 2 cited
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications
2024· 5 cited
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking
2024· 8 cited
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
IEEE Journal of Solid-State Circuits·2023· 9 cited
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS
2023· 9 cited
System and method for performing SRAM write assist
OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information)·2023Open Access
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
IEEE Journal of Solid-State Circuits·2023· 44 cited
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
IEEE Journal of Solid-State Circuits·2023· 45 cited
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
IEEE Transactions on Computers·2022· 19 citedOpen Access
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training
arXiv (Cornell University)·2022· 11 citedOpen Access
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 13 cited
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 13 cited
A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)·2022· 40 cited
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
2022· 7 cited
LNS-Madam: Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update
arXiv (Cornell University)·2021Open Access
Simba
Communications of the ACM·2021· 19 citedOpen Access
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
Proceedings of Machine Learning and Systems·2021· 2 cited
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
arXiv (Cornell University)·2021· 13 citedOpen Access
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Frequent Co-authors

William J. Dally(24), C. Thomas Gray(23), Stephen G. Tell(21), Brucek Khailany(17), Ben Keller(16), Rangharajan Venkatesan(14), Borivoje Nikolić(14), Sanquan Song(14), Nikola Nedovic(12), Matthew Fojtik(11), Krste Asanović(11), John W. Poulton(11), Walker J. Turner(11), John Wilson(10), Alicia Klinefelter(9), Nathaniel Pinckney(9), Yunsup Lee(9), Pi-Feng Chiu(9), Yakun Sophia Shao(8), Joel Emer(8)