Yen-Hao Shih

Macronix International (Taiwan) — Taiwan

Engineering · Physical Sciences

18h-index959citations48works0.02yr avg
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Research Topics

Semiconductor materials and devices(32), Advanced Data Storage Technologies(24), Advanced Memory and Neural Computing(11), Magnetic properties of thin films(8), Advancements in Semiconductor Devices and Circuit Design(8)

Publications48 total

Editorial Special Issue on “Memory Devices and Technologies for the Next Decade”
IEEE Transactions on Electron Devices·2020· 1 citedOpen Access
Design and Implementation of SPEEX Speech Technology on ARM Processor
Communications in computer and information science·2018
A promising solution to reduce plasma induced damage (PID) of high density plasma (HDP) oxide without sacrificing the gap-fill and throughput performance — Chin-Tsan Yeh
2017· 2 cited
Design and implement SPEEX decoder on ARM processor
2016· 4 cited
Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND
IEEE Transactions on Electron Devices·2016· 13 cited
A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
2015· 2 cited
Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations
IEEE Journal of Solid-State Circuits·2015· 37 cited
A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND
IEEE Electron Device Letters·2015· 5 cited
A novel double-trapping BE-SONOS charge-trapping NAND flash device to overcome the erase saturation without using curvature-induced field enhancement effect or high-K (HK)/metal gate (MG) materials
2014· 10 cited
Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture
2014· 21 cited
Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory
2014· 7 cited
A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory
2014· 3 cited
Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices
IEEE Transactions on Electron Devices·2014· 44 cited
Trapping-free string select transistors and ground select transistors for Vg-type 3D NAND Flash memory
2014· 2 cited
Study of the programming sequence induced back-pattern effect in split-page 3D vertical-gate (VG) NAND flash
2014· 12 cited
Distribution of nanoscale nuclei in the amorphous dome of a phase change random access memory
Applied Physics Letters·2014· 32 cited
A novel dual-channel 3D NAND flash featuring both N-channel and P-channel NAND characteristics for bit-alterable Flash memory and a new opportunity in sensing the stored charge in the WL space
2013· 22 cited
A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming
Symposium on VLSI Technology·2013· 7 cited
3D stackable vertical-gate BE-SONOS NAND flash with layer-aware program-and-read schemes and wave-propagation fail-bit-detection against cross-layer process variations
2013· 4 cited
Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage
Symposium on VLSI Technology·2013· 11 cited
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Frequent Co-authors

Hang-Ting Lue(31), Chih-Yuan Lu(23), Yi‐Hsuan Hsiao(17), Kuang-Yeu Hsieh(14), Chih‐Yuan Lu(13), Chih-Chang Hsieh(10), Pei-Ying Du(9), Wei-Chen Chen(9), Kuo-Pin Chang(9), Erh-Kun Lai(8), Tzu‐Hsuan Hsu(8), Chih‐Ping Chen(7), Tahone Yang(7), Kuo-Ping Chang(6), Kuang‐Chao Chen(5), Shih‐Hung Chen(5), Chun-Hsiung Hung(5), Yi‐Chou Chen(4), Chieh-Fang Chen(4), Shuo-Nan Hung(4)