Chih-Yuan Lu

Macronix International (Taiwan) — Taiwan

Engineering · Physical Sciences

23h-index2.1kcitations224works1.02yr avg
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Research Topics

Semiconductor materials and devices(154), Advanced Data Storage Technologies(71), Advancements in Semiconductor Devices and Circuit Design(67), Advanced Memory and Neural Computing(56), Integrated Circuits and Semiconductor Failure Analysis(36)

Publications220 total

Complementary Asymmetric Coding in Dichotomized Bitlines for High Bit-Per-Cell 3D NAND Flash Technology
IEEE Electron Device Letters·2025
Target Reprogramming for Tightening Threshold Voltage Distribution in Charge Trapping 3D NAND Flash Memory
IEEE Electron Device Letters·2025
A Recall-free 3D Stackable nvDRAM Built Upon Gate-Controlled Thyristor
2025· 1 cited
Performance Evaluation of 3D 1T-nC Ferroelectric RAM Architectures
2025
A Novel 3D Stacked Vertical-Channel High-Voltage Peripheral Transistor for Largely Scaled the WL Driver Circuit of 1000-layer 3D NAND Flash
2025
Utilizing 2T SONOS Cell Characteristics for L2/Euclidean Distance Computing - From Unit Cell to Array Operations
2025
A Novel BTBT Erase-Based PUF Generation Method With High Throughput in a 3-D <sub>NAND</sub> Flash Memory
IEEE Transactions on Electron Devices·2025· 1 cited
High Dimensional Analog Range In-3D-NAND Search Accelerator for Applications of Search in Few-Shot Learning Model and Retrieval in Retrieval Augmented Generation
2024
Analog In-Memory Search Technology Based on Automotive Grade NOR Flash Memory
2024
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs
2024· 8 cited
The Constraint Artificial-Intelligence Assisted Method for Etching Structure Optimization
2024· 1 cited
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL’s and Vertical BL for Better Cell Size Scaling and Array Selection
2024· 1 cited
Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide
2024· 1 cited
Reliability Assessment for an In-3D-NAND Approximate Searching Solution
2024· 1 cited
Deteriorated Non-Linear Interference in 3D NAND Cell With Word-Line Pitch Scaling Due to the Incapability to Turn on Non-Gate-Controlled Region
IEEE Electron Device Letters·2023· 8 cited
A Mixing-mode Matrix-Vector-Multiplication Architecture for Large-scale Perceptron Operation
2023· 1 cited
Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance
2023· 8 cited
A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device
2023· 6 cited
Common Source Line-to-Word Line Short Improvement by Eliminating SLT Sidewall Notch in 3D NAND Deep Trench Patterning
2023· 1 cited
A high-efficiency, reliable multilevel hardware-accelerated annealer with in-memory spin coupling and complementary read algorithm
Japanese Journal of Applied Physics·2023Open Access
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Frequent Co-authors

Hang-Ting Lue(30), Kuang-Yeu Hsieh(18), Yi‐Hsuan Hsiao(13), Chih-Chang Hsieh(13), Kuang‐Chao Chen(12), Pei-Ying Du(11), Yen-Hao Shih(11), Rich Liu(11), Tzu‐Hsuan Hsu(10), Tahone Yang(10), Erh-Kun Lai(8), Wei-Chen Chen(8), Kuo-Pin Chang(8), Szu-Yu Wang(8), Ling-Wu Yang(6), Wen-Jer Tsai(5), Tahui Wang(5), Chih‐Ping Chen(5), Sheng-Chih Lai(5), Keh-Chung Wang(5)