V. Dhandapani

KPR Institute of Engineering and Technology — India

Engineering · Physical Sciences

12h-index880citations28works0.02yr avg
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Research Topics

Advancements in Semiconductor Devices and Circuit Design(18), Semiconductor materials and devices(17), Integrated Circuits and Semiconductor Failure Analysis(14), Silicon and Solar Cell Technologies(5), Ferroelectric and Negative Capacitance Devices(4)

Publications28 total

OPTIMIZING BIDIRECTIONAL EV CHARGERS FOR RESILIENT VEHICLE-TO-GRID AND VEHICLE-TO-HOME ENERGY EXCHANGE
International Journal of Apllied Mathematics·2025Open Access
Optimizing switching sequences in AC-AC converters for enhanced safety and performance in conveyor systems
Scientific Reports·2025Open Access
Functionalized silicon substrates with stripe-patterned surface-near electrostatic forces for the self-organized, stable immobilization of biomolecules
Applied Surface Science·2020· 6 cited
Thermal Stability and Laser Annealing of Si$_{1-y}$C$_{y}$ alloys
Bulletin of the American Physical Society·2008
Characteristic Study of SOI eSiGe Techonology
Proceedings - IEEE International SOI Conference/Proceedings·2007
An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing
Proceedings - IEEE International SOI Conference/Proceedings·2007· 4 cited
Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts
Proceedings - IEEE International SOI Conference/Proceedings·2007· 2 cited
Uniaxial Strain Enhancement in SOI Technology for the Improvement of Channel and Exterior Resistances
ECS Transactions·2007
Uniaxial Strain Enhancement in SOI Technology for the Improvement of Channel and Exterior Resistances
ECS Meeting Abstracts·2007Open Access
Metrology Challenges for 45-nm Strained-Si Device Technology
IEEE Transactions on Semiconductor Manufacturing·2006· 17 cited
New Materials, Processes and Device Structures for 65nm CMOS Technology Node and Beyond
ECS Meeting Abstracts·2006Open Access
New Materials, Processes and Device Structures for 65nm CMOS Technology Node and Beyond
2006
Uniaxial and Biaxial Strain for CMOS Performance Enhancement
2006 International SiGe Technology and Device Meeting·2006· 3 cited
Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)
2006· 13 cited
Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement
2005· 24 cited
Integration challenges of new materials and device architectures for IC applications
2004· 2 cited
Fermi-Level Pinning at the Polysilicon/Metal–Oxide Interface—Part II
IEEE Transactions on Electron Devices·2004· 174 cited
Fermi-Level Pinning at the Polysilicon/Metal Oxide Interface—Part I
IEEE Transactions on Electron Devices·2004· 224 cited
Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]
2004· 20 cited
Fermi level pinning at the polySi/metal oxide interface
2004· 111 cited
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Frequent Co-authors

D. C. Gilmer(13), S. Samavedam(11), Dina H. Triyoso(10), R. Rai(10), J. Mogab(10), Bich-Yen Nguyen(10), R. I. Hegde(9), R. Garcia(9), Philip J. Tobin(9), L. Prabhu(9), Stefan Zollner(9), S. Venkatesan(9), H.‐H. Tseng(8), J. Schaeffer(8), L.B. La(8), T. White(8), J. Hildreth(8), D. Roan(7), Bruce White(7), D. Theodore(7)