R. Liu

University of Electronic Science and Technology of China — China

Engineering · Physical Sciences

11h-index568citations23works0.02yr avg
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Research Topics

Semiconductor materials and devices(20), Advanced Memory and Neural Computing(15), Advancements in Semiconductor Devices and Circuit Design(9), Ferroelectric and Negative Capacitance Devices(6), Advanced Data Storage Technologies(4)

Publications23 total

Joint pulse signal detection and DOA estimation algorithm based on eigenvalue distribution of sample autocorrelation matrix
IET conference proceedings.·2024
Unipolar Switching Behaviors of RTO $\hbox{WO}_{X}$ RRAM
IEEE Electron Device Letters·2010· 108 cited
Reliability issues of using barrier-engineered (BE) tunneling dielectric for floating gate flash memories
2009
Multi-Level Operation of Fully CMOS Compatible WOX Resistive Random Access Memory (RRAM)
2009· 25 cited
Pulse-$IV$ Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide
IEEE Electron Device Letters·2009· 1 cited
A critical review of charge-trapping NAND flash devices
2008· 15 cited
Multi-Level Switching Characteristics for WO<sub>X</sub> Resistive RAM (RRAM)
2008· 6 cited
Improved Reliability Performances of SONOS-Type Devices Using Hot-Hole Erase Method by Novel Negative FN Operations
IEEE Transactions on Device and Materials Reliability·2008· 1 cited
A novel buried-channel FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance
Symposium on VLSI Technology·2006· 6 cited
BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability
2006· 134 cited
A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory
2006· 26 cited
Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model
IEEE Transactions on Electron Devices·2005· 33 cited
AC-SONOS: a single-poly, assist-charge induced source-side-injection SONOS low power nonvolatile memory
2005
An Asymmetric Two-Side Program With One-Side Read (ATPOR) Device for MultiBit Per Cell MLC Nitride-Trapping Flash Memories
IEEE Transactions on Electron Devices·2005· 4 cited
Novel soft erase and re-fill methods for a P/sup +/-poly gate nitride trapping non-volatile memory device with excellent endurance and retention properties
2005· 24 cited
A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties
IEEE Electron Device Letters·2005· 4 cited
A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle endurance
2005· 23 cited
Mechanism for slow programming in advanced low-voltage, high-speed ferroelectric memory
2005
Investigation of Maximum Current Sensing Window for Two-Side Operation, Four-bit/cell MLC Nitride-Trapping Nonvolatile Flash Memories
IEEE Electron Device Letters·2004· 12 cited
A Transient Analysis Method to Characterize the Trap Vertical Location in Nitride-Trapping Devices
IEEE Electron Device Letters·2004· 51 cited
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Frequent Co-authors

Hang-Ting Lue(12), Kuang-Yeu Hsieh(9), Erh-Kun Lai(6), Chih‐Yuan Lu(6), Chih-Yuan Lu(6), K. Y. Hsieh(5), Sheng-Chih Lai(4), Yi‐Hsuan Hsiao(4), Yen-Hao Shih(3), Wei-Chih Chien(3), Y. D. Yao(3), Peng Lin(3), Jingjing Gong(3), Yang‐Hsin Shih(3), S.L. Lung(3), Tzu‐Hsuan Hsu(3), C.-Y. Lu(3), Pei-Ying Du(3), Szu-Yu Wang(2), Ling-Wu Yang(2)