S. Dakshina-Murthy

Engineering · Physical Sciences

7h-index230citations15works0.02yr avg
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Research Topics

Semiconductor materials and devices(11), Advancements in Photolithography Techniques(7), Integrated Circuits and Semiconductor Failure Analysis(7), Advancements in Semiconductor Devices and Circuit Design(5), Ferroelectric and Negative Capacitance Devices(2)

Publications15 total

An adaptive optimisation scheme for controlling air flow process with satisfactory transient performance
SHILAP Revista de lepidopterología·2010· 7 citedOpen Access
A Novel Approach for the Patterning and High-Volume Production of Sub-40-nm Gates
IEEE Transactions on Semiconductor Manufacturing·2005· 20 cited
Dual-metal gate CMOS with HfO/sub 2/ gate dielectric
2003· 37 cited
Metal gate MOSFETs with HfO/sub 2/ gate dielectric
2003· 9 cited
Fabrication of integrated circuits with high yield using ultra-thin resist processes
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2003· 2 cited
Controlling line-edge rougness to within reasonable limits
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2003· 6 cited
Model of Photoresist Trimming Using CF_4/O 2 Plasma
APS March Meeting Abstracts·2003
Finfet with isolated n+ and p+ gate regions strapped with metal and polysilicon
2003· 8 cited
Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics
Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena·2002· 100 cited
Partial trench isolated body-tied (PTIBT) structure for SOI applications
2002· 1 cited
Integration of UTR processes into MPU IC manufacturing flows
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2002· 7 cited
CMOS-compatible planar silicon waveguide-grating-coupler photodetectors fabricated on silicon-on-insulator (SOI) substrates
IEEE Journal of Quantum Electronics·2002· 23 cited
Evaluation of Candidate Metals for Dual-Metal Gate CMOS with HfO<sub>2</sub> Gate Dielectric
MRS Proceedings·2002· 6 cited
Integration of ultrathin resist processes into MPU IC manufacturing flows
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·2001· 2 cited
Comparison of binary mask defect printability analysis using virtual stepper system and aerial image microscope system
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE·1999· 2 cited

Frequent Co-authors

J. Schaeffer(5), J. Mogab(5), Ana María Miranda Zavala(5), S. Samavedam(4), D. C. Gilmer(4), V. Dhandapani(4), R. Martín(4), L.B. La(4), James A. Smith(4), E. Luckowski(4), T. Stephens(4), Jonathan Cobb(4), Colita Parker(4), Philip J. Tobin(3), Bich-Yen Nguyen(3), Richard D. Peters(3), Wei Wu(3), Scott D. Hector(3), B. E. White(2), Z.X. Jiang(2)